#ifndef __DEV_UREG_H__
#define __DEV_UREG_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************USB_PHY_CTRL0***********************************/
#define DEV_UREG_USB_PHY_CTRL0_PULLDMDN_DISABLE                 (0x0UL<<28)
#define DEV_UREG_USB_PHY_CTRL0_PULLDMDN_ENABLE                  (0x1UL<<28)
#define DEV_UREG_USB_PHY_CTRL0_PULLDMDN_MASK                    (0x1UL<<28)
#define DEV_UREG_USB_PHY_CTRL0_PULLDPDN_DISABLE                 (0x0UL<<27)
#define DEV_UREG_USB_PHY_CTRL0_PULLDPDN_ENABLE                  (0x1UL<<27)
#define DEV_UREG_USB_PHY_CTRL0_PULLDPDN_MASK                    (0x1UL<<27)
#define DEV_UREG_USB_PHY_CTRL0_DIV_INT_I_MASK                   (0x1ffUL<<16)
#define DEV_UREG_USB_PHY_CTRL0_HSZR_CNTL_55OHMS                 (0x0UL<<12)
#define DEV_UREG_USB_PHY_CTRL0_HSZR_CNTL_49OHMS                 (0x1UL<<12)
#define DEV_UREG_USB_PHY_CTRL0_HSZR_CNTL_44OHMS                 (0x3UL<<12)
#define DEV_UREG_USB_PHY_CTRL0_HSZR_CNTL_40OHMS                 (0x7UL<<12)
#define DEV_UREG_USB_PHY_CTRL0_HSZR_CNTL_37OHMS                 (0xfUL<<12)
#define DEV_UREG_USB_PHY_CTRL0_HSZR_CNTL_MASK                   (0xfUL<<12)
#define DEV_UREG_USB_PHY_CTRL0_FSZR_CNTL_55OHMS                 (0x0UL<<8)
#define DEV_UREG_USB_PHY_CTRL0_FSZR_CNTL_49OHMS                 (0x1UL<<8)
#define DEV_UREG_USB_PHY_CTRL0_FSZR_CNTL_44OHMS                 (0x3UL<<8)
#define DEV_UREG_USB_PHY_CTRL0_FSZR_CNTL_40OHMS                 (0x7UL<<8)
#define DEV_UREG_USB_PHY_CTRL0_FSZR_CNTL_37OHMS                 (0xfUL<<8)
#define DEV_UREG_USB_PHY_CTRL0_FSZR_CNTL_MASK                   (0xfUL<<8)
#define DEV_UREG_USB_PHY_CTRL0_DIV_VALUE_SEL_HARDWAREMODE       (0x0UL<<7)
#define DEV_UREG_USB_PHY_CTRL0_DIV_VALUE_SEL_SOFTWAREMODE       (0x1UL<<7)
#define DEV_UREG_USB_PHY_CTRL0_DIV_VALUE_SEL_MASK               (0x1UL<<7)
#define DEV_UREG_USB_PHY_CTRL0_SIM_FAST                         (0x1UL<<6)
#define DEV_UREG_USB_PHY_CTRL0_SELF_TEST                        (0x1UL<<5)
#define DEV_UREG_USB_PHY_CTRL0_DIV_TRIM_EN                      (0x1UL<<4)
#define DEV_UREG_USB_PHY_CTRL0_CLK_SEL_INNEROSC                 (0x0UL<<3)
#define DEV_UREG_USB_PHY_CTRL0_CLK_SEL_CLK12M                   (0x1UL<<3)
#define DEV_UREG_USB_PHY_CTRL0_CLK_SEL_MASK                     (0x1UL<<3)
#define DEV_UREG_USB_PHY_CTRL0_PLL_EN                           (0x1UL<<2)
#define DEV_UREG_USB_PHY_CTRL0_EN_PHY_POWEROFF                  (0x0UL<<1)
#define DEV_UREG_USB_PHY_CTRL0_EN_PHY_POWERON                   (0x1UL<<1)
#define DEV_UREG_USB_PHY_CTRL0_EN_PHY_MASK                      (0x1UL<<1)
#define DEV_UREG_USB_PHY_CTRL0_RESET_WORKING                    (0x0UL<<0)
#define DEV_UREG_USB_PHY_CTRL0_RESET_RESET                      (0x1UL<<0)
#define DEV_UREG_USB_PHY_CTRL0_RESET_MASK                       (0x1UL<<0)
/****USB_PHY_CTRL0 end****/


/***********************************USB_PHY_CTRL1***********************************/
#define DEV_UREG_USB_PHY_CTRL1_FRAC_EN_I_DISABLE                (0x0UL<<21)
#define DEV_UREG_USB_PHY_CTRL1_FRAC_EN_I_ENABLE                 (0x1UL<<21)
#define DEV_UREG_USB_PHY_CTRL1_FRAC_EN_I_MASK                   (0x1UL<<21)
#define DEV_UREG_USB_PHY_CTRL1_DIV_FRAC_I_MASK                  (0x1fffffUL<<0)
/****USB_PHY_CTRL1 end****/


/***********************************USB_PHY_CTRL2***********************************/
#define DEV_UREG_USB_PHY_CTRL2_VSTATUS_MASK                     (0xffffffffUL<<0)
/****USB_PHY_CTRL2 end****/


/***********************************USB_PLL_CTRL***********************************/
#define DEV_UREG_USB_PLL_CTRL_OSC_USB_DIV_1                     (0x0UL<<29)
#define DEV_UREG_USB_PLL_CTRL_OSC_USB_DIV_2                     (0x1UL<<29)
#define DEV_UREG_USB_PLL_CTRL_OSC_USB_DIV_MASK                  (0x1UL<<29)
#define DEV_UREG_USB_PLL_CTRL_OSC_USB_SEL_XCLK                  (0x0UL<<28)
#define DEV_UREG_USB_PLL_CTRL_OSC_USB_SEL_RC64M                 (0x1UL<<28)
#define DEV_UREG_USB_PLL_CTRL_OSC_USB_SEL_MASK                  (0x1UL<<28)
#define DEV_UREG_USB_PLL_CTRL_PLL_USB_EN                        (0x1UL<<26)
#define DEV_UREG_USB_PLL_CTRL_OSC_USB_EN                        (0x1UL<<25)
#define DEV_UREG_USB_PLL_CTRL_USB_SOF_EN                        (0x1UL<<24)
#define DEV_UREG_USB_PLL_CTRL_RC32M_CTUNE_MASK                  (0x7fUL<<16)
#define DEV_UREG_USB_PLL_CTRL_ICP_SEL_0_5UA                     (0x0UL<<10)
#define DEV_UREG_USB_PLL_CTRL_ICP_SEL_1UA                       (0x1UL<<10)
#define DEV_UREG_USB_PLL_CTRL_ICP_SEL_1_5UA                     (0x2UL<<10)
#define DEV_UREG_USB_PLL_CTRL_ICP_SEL_2UA                       (0x3UL<<10)
#define DEV_UREG_USB_PLL_CTRL_ICP_SEL_2_5UA                     (0x4UL<<10)
#define DEV_UREG_USB_PLL_CTRL_ICP_SEL_3UA                       (0x5UL<<10)
#define DEV_UREG_USB_PLL_CTRL_ICP_SEL_3_5UA                     (0x6UL<<10)
#define DEV_UREG_USB_PLL_CTRL_ICP_SEL_4UA                       (0x7UL<<10)
#define DEV_UREG_USB_PLL_CTRL_ICP_SEL_MASK                      (0x7UL<<10)
#define DEV_UREG_USB_PLL_CTRL_REG_VCO_LV_MASK                   (0x3UL<<8)
#define DEV_UREG_USB_PLL_CTRL_DITHER_BIT_BIT0                   (0x0UL<<5)
#define DEV_UREG_USB_PLL_CTRL_DITHER_BIT_BIT1                   (0x1UL<<5)
#define DEV_UREG_USB_PLL_CTRL_DITHER_BIT_MASK                   (0x1UL<<5)
#define DEV_UREG_USB_PLL_CTRL_DITHER_EN_DISABLE                 (0x0UL<<4)
#define DEV_UREG_USB_PLL_CTRL_DITHER_EN_ENABLE                  (0x1UL<<4)
#define DEV_UREG_USB_PLL_CTRL_DITHER_EN_MASK                    (0x1UL<<4)
#define DEV_UREG_USB_PLL_CTRL_LOCK_TIME_32_TDELAY               (0x0UL<<2)
#define DEV_UREG_USB_PLL_CTRL_LOCK_TIME_128_TDELAY              (0x1UL<<2)
#define DEV_UREG_USB_PLL_CTRL_LOCK_TIME_256_TDELAY              (0x2UL<<2)
#define DEV_UREG_USB_PLL_CTRL_LOCK_TIME_512_TDELAY              (0x3UL<<2)
#define DEV_UREG_USB_PLL_CTRL_LOCK_TIME_MASK                    (0x3UL<<2)
#define DEV_UREG_USB_PLL_CTRL_DELAY_X1_2NS                      (0x0UL<<1)
#define DEV_UREG_USB_PLL_CTRL_DELAY_X1_4NS                      (0x1UL<<1)
#define DEV_UREG_USB_PLL_CTRL_DELAY_X1_MASK                     (0x1UL<<1)
#define DEV_UREG_USB_PLL_CTRL_FORCE_LOCK_NOTBYPASS              (0x0UL<<0)
#define DEV_UREG_USB_PLL_CTRL_FORCE_LOCK_BYPASS                 (0x1UL<<0)
#define DEV_UREG_USB_PLL_CTRL_FORCE_LOCK_MASK                   (0x1UL<<0)
/****USB_PLL_CTRL end****/


/***********************************USB_DBG_CTRL0***********************************/
#define DEV_UREG_USB_DBG_CTRL0_DEBUG3_MASK                      (0xffUL<<24)
#define DEV_UREG_USB_DBG_CTRL0_DEBUG2_MASK                      (0xffUL<<16)
#define DEV_UREG_USB_DBG_CTRL0_DEBUG1_MASK                      (0xffUL<<8)
#define DEV_UREG_USB_DBG_CTRL0_DEBUG0_MASK                      (0xffUL<<0)
/****USB_DBG_CTRL0 end****/


/***********************************USB_DBG_CTRL1***********************************/
#define DEV_UREG_USB_DBG_CTRL1_DEBUG4_MASK                      (0xffUL<<0)
/****USB_DBG_CTRL1 end****/


/***********************************USB_PHY_STAT0***********************************/
#define DEV_UREG_USB_PHY_STAT0_DIV_INT_O_MASK                   (0x7ffUL<<16)
#define DEV_UREG_USB_PHY_STAT0_BIST_PASS                        (0x1UL<<2)
#define DEV_UREG_USB_PHY_STAT0_TRIM_LOCK                        (0x1UL<<1)
#define DEV_UREG_USB_PHY_STAT0_CLK_STATE                        (0x1UL<<0)
/****USB_PHY_STAT0 end****/


/***********************************USB_PHY_STAT1***********************************/
#define DEV_UREG_USB_PHY_STAT1_DIV_FRAC_O_MASK                  (0x1fffffUL<<0)
/****USB_PHY_STAT1 end****/


/***********************************USB_CTR_BIST0***********************************/
#define DEV_UREG_USB_CTR_BIST0_PHY_FAKE_CRC0_MASK               (0xffUL<<24)
#define DEV_UREG_USB_CTR_BIST0_PHY_FAKE_CRC1_MASK               (0xffUL<<16)
#define DEV_UREG_USB_CTR_BIST0_PHY_FAKE_REQ                     (0x1UL<<15)
#define DEV_UREG_USB_CTR_BIST0_PHY_FAKE_ADDR_MASK               (0x7fUL<<8)
#define DEV_UREG_USB_CTR_BIST0_PHY_FAKE_EN                      (0x1UL<<7)
#define DEV_UREG_USB_CTR_BIST0_PHY_FAKE_ENDP_MASK               (0x3UL<<5)
#define DEV_UREG_USB_CTR_BIST0_PHY_FAKE_CRC2_MASK               (0x1fUL<<0)
/****USB_CTR_BIST0 end****/


/***********************************USB_CTR_BIST1***********************************/
#define DEV_UREG_USB_CTR_BIST1_PHY_FAKE_data3_MASK              (0xffUL<<24)
#define DEV_UREG_USB_CTR_BIST1_PHY_FAKE_data2_MASK              (0xffUL<<16)
#define DEV_UREG_USB_CTR_BIST1_PHY_FAKE_data1_MASK              (0xffUL<<8)
#define DEV_UREG_USB_CTR_BIST1_PHY_FAKE_data0_MASK              (0xffUL<<0)
/****USB_CTR_BIST1 end****/


/***********************************USB_CTR_BIST2***********************************/
#define DEV_UREG_USB_CTR_BIST2_PHY_FAKE_data7_MASK              (0xffUL<<24)
#define DEV_UREG_USB_CTR_BIST2_PHY_FAKE_data6_MASK              (0xffUL<<16)
#define DEV_UREG_USB_CTR_BIST2_PHY_FAKE_data5_MASK              (0xffUL<<8)
#define DEV_UREG_USB_CTR_BIST2_PHY_FAKE_data4_MASK              (0xffUL<<0)
/****USB_CTR_BIST2 end****/


/***********************************DEV_UREG register***********************************/
typedef struct
{

    __IO    uint32_t    USB_PHY_CTRL0;                           /* 0x0    USB PHY Control0 */
    __IO    uint32_t    USB_PHY_CTRL1;                           /* 0x4    USB PHY Control1 */
    __IO    uint32_t    USB_PHY_CTRL2;                           /* 0x8    USB PHY Control2 */
    __IO    uint32_t    USB_PLL_CTRL;                            /* 0xc    USB PLL Control */
    __IO    uint32_t    USB_DBG_CTRL0;                           /* 0x10    USB Debug Control0 */
    __IO    uint32_t    USB_DBG_CTRL1;                           /* 0x14    USB Debug Control1 */
    __I     uint32_t    USB_PHY_STAT0;                           /* 0x18    USB PHY Status0 */
    __I     uint32_t    USB_PHY_STAT1;                           /* 0x1c    USB PHY Status1 */
    __IO    uint32_t    USB_CTR_BIST0;                           /* 0x20    USB controller BIST signal part 1 */
    __IO    uint32_t    USB_CTR_BIST1;                           /* 0x24    USB controller BIST signal part 2 */
    __IO    uint32_t    USB_CTR_BIST2;                           /* 0x28    USB controller BIST signal part3 */
} DEV_UREG_RegDef;
/****DEV_UREG end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
