#ifndef __AON_GPIO_H__
#define __AON_GPIO_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************SPIOn_CTL***********************************/
#define AON_GPIO_SPIOn_CTL_IV_DISABLE                           (0x0UL<<14)
#define AON_GPIO_SPIOn_CTL_IV_ENABLE                            (0x1UL<<14)
#define AON_GPIO_SPIOn_CTL_IV_MASK                              (0x1UL<<14)
#define AON_GPIO_SPIOn_CTL_OV_DISABLE                           (0x0UL<<13)
#define AON_GPIO_SPIOn_CTL_OV_ENABLE                            (0x1UL<<13)
#define AON_GPIO_SPIOn_CTL_OV_MASK                              (0x1UL<<13)
#define AON_GPIO_SPIOn_CTL_DS                                   (0x1UL<<12)
#define AON_GPIO_SPIOn_CTL_LB_DISABLE                           (0x0UL<<10)
#define AON_GPIO_SPIOn_CTL_LB_ENABLE                            (0x1UL<<10)
#define AON_GPIO_SPIOn_CTL_LB_MASK                              (0x1UL<<10)
#define AON_GPIO_SPIOn_CTL_O                                    (0x1UL<<9)
#define AON_GPIO_SPIOn_CTL_PS_PULLDOWN                          (0x0UL<<7)
#define AON_GPIO_SPIOn_CTL_PS_PULLUP                            (0x1UL<<7)
#define AON_GPIO_SPIOn_CTL_PS_MASK                              (0x1UL<<7)
#define AON_GPIO_SPIOn_CTL_PE_DISABLE                           (0x0UL<<6)
#define AON_GPIO_SPIOn_CTL_PE_ENABLE                            (0x1UL<<6)
#define AON_GPIO_SPIOn_CTL_PE_MASK                              (0x1UL<<6)
#define AON_GPIO_SPIOn_CTL_IE_DISABLE                           (0x0UL<<5)
#define AON_GPIO_SPIOn_CTL_IE_ENABLE                            (0x1UL<<5)
#define AON_GPIO_SPIOn_CTL_IE_MASK                              (0x1UL<<5)
#define AON_GPIO_SPIOn_CTL_OE_DISABLE                           (0x0UL<<4)
#define AON_GPIO_SPIOn_CTL_OE_ENABLE                            (0x1UL<<4)
#define AON_GPIO_SPIOn_CTL_OE_MASK                              (0x1UL<<4)
#define AON_GPIO_SPIOn_CTL_MFP_MASK                             (0xfUL<<0)
/****SPIOn_CTL end****/


/***********************************SPIO_IN***********************************/
#define AON_GPIO_SPIO_IN_MASK                                   (0x3fUL<<0)
/****SPIO_IN end****/


/***********************************SPIO_IC***********************************/
#define AON_GPIO_SPIO_IC_EVENT_NONE                             (0x0UL<<4)
#define AON_GPIO_SPIO_IC_EVENT_RISE                             (0x1UL<<4)
#define AON_GPIO_SPIO_IC_EVENT_FALL                             (0x2UL<<4)
#define AON_GPIO_SPIO_IC_EVENT_BOTHEDGE                         (0x3UL<<4)
#define AON_GPIO_SPIO_IC_EVENT_HIGH                             (0x4UL<<4)
#define AON_GPIO_SPIO_IC_EVENT_LOW                              (0x5UL<<4)
#define AON_GPIO_SPIO_IC_EVENT_MASK                             (0x7UL<<4)
#define AON_GPIO_SPIO_IC_SOURCE_MASK                            (0xfUL<<0)
/****SPIO_IC end****/


/***********************************SPIO_ONOFF2***********************************/
#define AON_GPIO_SPIO_ONOFF2_SOURCE_MASK                        (0x7UL<<0)
/****SPIO_ONOFF2 end****/


/***********************************DBIO_CTL***********************************/
#define AON_GPIO_DBIO_CTL_BIT_SEL_MASK                          (0xfUL<<8)
#define AON_GPIO_DBIO_CTL_BIT_EN                                (0x1UL<<7)
#define AON_GPIO_DBIO_CTL_GRP_SEL_MASK                          (0x3fUL<<0)
/****DBIO_CTL end****/


/***********************************DBIO_OE0***********************************/
#define AON_GPIO_DBIO_OE0_MASK                                  (0x3fUL<<0)
/****DBIO_OE0 end****/


/***********************************DBIO_IE0***********************************/
#define AON_GPIO_DBIO_IE0_MASK                                  (0x3fUL<<0)
/****DBIO_IE0 end****/


/***********************************AON_GPIO register***********************************/
typedef struct
{

    __IO    uint32_t    SPIOn_CTL[6];                            /* 0x0    SPIO Control */
    uint32_t    RESERVED0[2];
    __I     uint32_t    SPIO_IN;                                 /* 0x20    SPIO Input */
    uint32_t    RESERVED1[7];
    __IO    uint32_t    SPIO_IC;                                 /* 0x40    SPIO Interrupt Control */
    __IO    uint32_t    SPIO_ONOFF2;                             /* 0x44    SPIO ONOFF Control */
    uint32_t    RESERVED2[6];
    __IO    uint32_t    DBIO_CTL;                                /* 0x60    Debug IO Control */
    __IO    uint32_t    DBIO_OE0;                                /* 0x64    Debug IO Output Enable */
    __IO    uint32_t    DBIO_IE0;                                /* 0x68    Debug IO Input Enable */
} AON_GPIO_RegDef;
/****AON_GPIO end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
