#ifndef __DEV_UREG_FIELD_H__
#define __DEV_UREG_FIELD_H__

#include "sp2cw3.h"
/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************SB_PHY_CTRL0***********************************/
typedef struct
{

    __IO uint32_t RESET               : 1;
    __IO uint32_t EN_PHY              : 1;
    __IO uint32_t PLL_EN              : 1;
    __IO uint32_t CLK_SEL             : 1;
    __IO uint32_t DIV_TRIM_EN         : 1;
    __IO uint32_t SELF_TEST           : 1;
    __IO uint32_t SIM_FAST            : 1;
    __IO uint32_t DIV_VALUE_SEL       : 1;
    __IO uint32_t FSZR_CNTL           : 4;
    __IO uint32_t HSZR_CNTL           : 4;
    __IO uint32_t DIV_INT_I           : 9;
    uint32_t RESERVED0           : 2;
    __IO uint32_t PULLDPDN            : 1;
    __IO uint32_t PULLDMDN            : 1;
    uint32_t RESERVED1           : 3;
} DEV_UREG_SB_PHY_CTRL0_Field;
/****DEV_UREGSB_PHY_CTRL0 end****/

/***********************************SB_PHY_CTRL1***********************************/
typedef struct
{

    __IO uint32_t DIV_FRAC_I          : 21;
    __IO uint32_t FRAC_EN_I           : 1;
    uint32_t RESERVED0           : 10;
} DEV_UREG_SB_PHY_CTRL1_Field;
/****DEV_UREGSB_PHY_CTRL1 end****/

/***********************************SB_PHY_CTRL2***********************************/
typedef struct
{

    __IO uint32_t VSTATUS             : 32;
} DEV_UREG_SB_PHY_CTRL2_Field;
/****DEV_UREGSB_PHY_CTRL2 end****/

/***********************************SB_PLL_CTRL***********************************/
typedef struct
{

    __IO uint32_t FORCE_LOCK          : 1;
    __IO uint32_t DELAY_X1            : 1;
    __IO uint32_t LOCK_TIME           : 2;
    __IO uint32_t DITHER_EN           : 1;
    __IO uint32_t DITHER_BIT          : 1;
    uint32_t RESERVED0           : 2;
    __IO uint32_t REG_VCO_LV          : 2;
    __IO uint32_t ICP_SEL             : 3;
    uint32_t RESERVED1           : 3;
    __IO uint32_t RC32M_CTUNE         : 7;
    uint32_t RESERVED2           : 1;
    __IO uint32_t USB_SOF_EN          : 1;
    __IO uint32_t OSC_USB_EN          : 1;
    __IO uint32_t PLL_USB_EN          : 1;
    uint32_t RESERVED3           : 1;
    __IO uint32_t OSC_USB_SEL         : 1;
    __IO uint32_t OSC_USB_DIV         : 1;
    uint32_t RESERVED4           : 2;
} DEV_UREG_SB_PLL_CTRL_Field;
/****DEV_UREGSB_PLL_CTRL end****/

/***********************************SB_DBG_CTRL0***********************************/
typedef struct
{

    __IO uint32_t DEBUG0              : 8;
    __IO uint32_t DEBUG1              : 8;
    __IO uint32_t DEBUG2              : 8;
    __IO uint32_t DEBUG3              : 8;
} DEV_UREG_SB_DBG_CTRL0_Field;
/****DEV_UREGSB_DBG_CTRL0 end****/

/***********************************SB_DBG_CTRL1***********************************/
typedef struct
{

    __IO uint32_t DEBUG4              : 8;
    uint32_t RESERVED0           : 24;
} DEV_UREG_SB_DBG_CTRL1_Field;
/****DEV_UREGSB_DBG_CTRL1 end****/

/***********************************SB_PHY_STAT0***********************************/
typedef struct
{

    __I  uint32_t CLK_STATE           : 1;
    __I  uint32_t TRIM_LOCK           : 1;
    __I  uint32_t BIST_PASS           : 1;
    uint32_t RESERVED0           : 13;
    __I  uint32_t DIV_INT_O           : 11;
    uint32_t RESERVED1           : 5;
} DEV_UREG_SB_PHY_STAT0_Field;
/****DEV_UREGSB_PHY_STAT0 end****/

/***********************************SB_PHY_STAT1***********************************/
typedef struct
{

    __I  uint32_t DIV_FRAC_O          : 21;
    uint32_t RESERVED0           : 11;
} DEV_UREG_SB_PHY_STAT1_Field;
/****DEV_UREGSB_PHY_STAT1 end****/

/***********************************SB_CTR_BIST0***********************************/
typedef struct
{

    __IO uint32_t PHY_FAKE_CRC2       : 5;
    __IO uint32_t PHY_FAKE_ENDP       : 2;
    __IO uint32_t PHY_FAKE_EN         : 1;
    __IO uint32_t PHY_FAKE_ADDR       : 7;
    __IO uint32_t PHY_FAKE_REQ        : 1;
    __IO uint32_t PHY_FAKE_CRC1       : 8;
    __IO uint32_t PHY_FAKE_CRC0       : 8;
} DEV_UREG_SB_CTR_BIST0_Field;
/****DEV_UREGSB_CTR_BIST0 end****/

/***********************************SB_CTR_BIST1***********************************/
typedef struct
{

    __IO uint32_t PHY_FAKE_data0      : 8;
    __IO uint32_t PHY_FAKE_data1      : 8;
    __IO uint32_t PHY_FAKE_data2      : 8;
    __IO uint32_t PHY_FAKE_data3      : 8;
} DEV_UREG_SB_CTR_BIST1_Field;
/****DEV_UREGSB_CTR_BIST1 end****/

/***********************************SB_CTR_BIST2***********************************/
typedef struct
{

    __IO uint32_t PHY_FAKE_data4      : 8;
    __IO uint32_t PHY_FAKE_data5      : 8;
    __IO uint32_t PHY_FAKE_data6      : 8;
    __IO uint32_t PHY_FAKE_data7      : 8;
} DEV_UREG_SB_CTR_BIST2_Field;
/****DEV_UREGSB_CTR_BIST2 end****/

/***********************************DEV_UREG register***********************************/
typedef struct
{

    union
    {
        __IO    uint32_t    USB_PHY_CTRL0;                           /* 0x0    USB PHY Control0 */
        DEV_UREG_SB_PHY_CTRL0_Field    USB_PHY_CTRL0_f;
    };
    union
    {
        __IO    uint32_t    USB_PHY_CTRL1;                           /* 0x4    USB PHY Control1 */
        DEV_UREG_SB_PHY_CTRL1_Field    USB_PHY_CTRL1_f;
    };
    union
    {
        __IO    uint32_t    USB_PHY_CTRL2;                           /* 0x8    USB PHY Control2 */
        DEV_UREG_SB_PHY_CTRL2_Field    USB_PHY_CTRL2_f;
    };
    union
    {
        __IO    uint32_t    USB_PLL_CTRL;                            /* 0xc    USB PLL Control */
        DEV_UREG_SB_PLL_CTRL_Field    USB_PLL_CTRL_f;
    };
    union
    {
        __IO    uint32_t    USB_DBG_CTRL0;                           /* 0x10    USB Debug Control0 */
        DEV_UREG_SB_DBG_CTRL0_Field    USB_DBG_CTRL0_f;
    };
    union
    {
        __IO    uint32_t    USB_DBG_CTRL1;                           /* 0x14    USB Debug Control1 */
        DEV_UREG_SB_DBG_CTRL1_Field    USB_DBG_CTRL1_f;
    };
    union
    {
        __I     uint32_t    USB_PHY_STAT0;                           /* 0x18    USB PHY Status0 */
        DEV_UREG_SB_PHY_STAT0_Field    USB_PHY_STAT0_f;
    };
    union
    {
        __I     uint32_t    USB_PHY_STAT1;                           /* 0x1c    USB PHY Status1 */
        DEV_UREG_SB_PHY_STAT1_Field    USB_PHY_STAT1_f;
    };
    union
    {
        __IO    uint32_t    USB_CTR_BIST0;                           /* 0x20    USB controller BIST signal part 1 */
        DEV_UREG_SB_CTR_BIST0_Field    USB_CTR_BIST0_f;
    };
    union
    {
        __IO    uint32_t    USB_CTR_BIST1;                           /* 0x24    USB controller BIST signal part 2 */
        DEV_UREG_SB_CTR_BIST1_Field    USB_CTR_BIST1_f;
    };
    union
    {
        __IO    uint32_t    USB_CTR_BIST2;                           /* 0x28    USB controller BIST signal part3 */
        DEV_UREG_SB_CTR_BIST2_Field    USB_CTR_BIST2_f;
    };
} DEV_UREG_RegDef_f;
/****DEV_UREG end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
