#ifndef __AON_LRADC_H__
#define __AON_LRADC_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************LRADC_CFGn***********************************/
#define AON_LRADC_CFGn_SVK_EDGE_NONE                            (0x0UL<<20)
#define AON_LRADC_CFGn_SVK_EDGE_RISE                            (0x1UL<<20)
#define AON_LRADC_CFGn_SVK_EDGE_FALL                            (0x2UL<<20)
#define AON_LRADC_CFGn_SVK_EDGE_BOTHEDGE                        (0x3UL<<20)
#define AON_LRADC_CFGn_SVK_EDGE_HIGH                            (0x4UL<<20)
#define AON_LRADC_CFGn_SVK_EDGE_LOW                             (0x5UL<<20)
#define AON_LRADC_CFGn_SVK_EDGE_MASK                            (0x7UL<<20)
#define AON_LRADC_CFGn_SVK_TYPE_LRADC                           (0x0UL<<19)
#define AON_LRADC_CFGn_SVK_TYPE_LPCMP                           (0x1UL<<19)
#define AON_LRADC_CFGn_SVK_TYPE_MASK                            (0x1UL<<19)
#define AON_LRADC_CFGn_SVK_EN_DISABLE                           (0x0UL<<18)
#define AON_LRADC_CFGn_SVK_EN_ENABLE                            (0x1UL<<18)
#define AON_LRADC_CFGn_SVK_EN_MASK                              (0x1UL<<18)
#define AON_LRADC_CFGn_SVK_LVL_MASK                             (0x3ffUL<<8)
#define AON_LRADC_CFGn_AVG_1SAMPLE                              (0x0UL<<4)
#define AON_LRADC_CFGn_AVG_2SAMPLE                              (0x1UL<<4)
#define AON_LRADC_CFGn_AVG_4SAMPLE                              (0x2UL<<4)
#define AON_LRADC_CFGn_AVG_8SAMPLE                              (0x3UL<<4)
#define AON_LRADC_CFGn_AVG_16SAMPLE                             (0x4UL<<4)
#define AON_LRADC_CFGn_AVG_32SAMPLE                             (0x5UL<<4)
#define AON_LRADC_CFGn_AVG_MASK                                 (0x7UL<<4)
#define AON_LRADC_CFGn_SR_1                                     (0x0UL<<2)
#define AON_LRADC_CFGn_SR_2                                     (0x1UL<<2)
#define AON_LRADC_CFGn_SR_4                                     (0x2UL<<2)
#define AON_LRADC_CFGn_SR_8                                     (0x3UL<<2)
#define AON_LRADC_CFGn_SR_MASK                                  (0x3UL<<2)
#define AON_LRADC_CFGn_MODE_SINGLEMODE                          (0x0UL<<1)
#define AON_LRADC_CFGn_MODE_CONTINUEMODE                        (0x1UL<<1)
#define AON_LRADC_CFGn_MODE_MASK                                (0x1UL<<1)
#define AON_LRADC_CFGn_EN_DISABLE                               (0x0UL<<0)
#define AON_LRADC_CFGn_EN_ENABLE                                (0x1UL<<0)
#define AON_LRADC_CFGn_EN_MASK                                  (0x1UL<<0)
/****LRADC_CFGn end****/


/***********************************LRADC_ANA***********************************/
#define AON_LRADC_ANA_LRADC_VREF_SEL_LOWPOWERVREF               (0x0UL<<8)
#define AON_LRADC_ANA_LRADC_VREF_SEL_HIGHPERFORMANCEVREF        (0x1UL<<8)
#define AON_LRADC_ANA_LRADC_VREF_SEL_MASK                       (0x1UL<<8)
#define AON_LRADC_ANA_LRADC_MIC_LINEIN                          (0x0UL<<7)
#define AON_LRADC_ANA_LRADC_MIC_MICIN                           (0x1UL<<7)
#define AON_LRADC_ANA_LRADC_MIC_MASK                            (0x1UL<<7)
#define AON_LRADC_ANA_LRADC_PGA_18_0DB                          (0x0UL<<4)
#define AON_LRADC_ANA_LRADC_PGA_21_5DB                          (0x1UL<<4)
#define AON_LRADC_ANA_LRADC_PGA_25_0DB                          (0x2UL<<4)
#define AON_LRADC_ANA_LRADC_PGA_28_5DB                          (0x3UL<<4)
#define AON_LRADC_ANA_LRADC_PGA_32_0DB                          (0x4UL<<4)
#define AON_LRADC_ANA_LRADC_PGA_35_5DB                          (0x5UL<<4)
#define AON_LRADC_ANA_LRADC_PGA_39_0DB                          (0x6UL<<4)
#define AON_LRADC_ANA_LRADC_PGA_42_5DB                          (0x7UL<<4)
#define AON_LRADC_ANA_LRADC_PGA_MASK                            (0x7UL<<4)
#define AON_LRADC_ANA_LPCMP_VOL_500MV                           (0x0UL<<2)
#define AON_LRADC_ANA_LPCMP_VOL_950MV                           (0x1UL<<2)
#define AON_LRADC_ANA_LPCMP_VOL_MASK                            (0x1UL<<2)
#define AON_LRADC_ANA_LPCMP_EN                                  (0x1UL<<1)
#define AON_LRADC_ANA_LRADC_EN                                  (0x1UL<<0)
/****LRADC_ANA end****/


/***********************************LRADC_MKV0***********************************/
#define AON_LRADC_MKV0_KEY_THD1_MASK                            (0x3ffUL<<20)
#define AON_LRADC_MKV0_KEY_THD0_MASK                            (0x3ffUL<<10)
#define AON_LRADC_MKV0_KEY_SRC_LRADC00                          (0x0UL<<4)
#define AON_LRADC_MKV0_KEY_SRC_LRADC01                          (0x1UL<<4)
#define AON_LRADC_MKV0_KEY_SRC_LRADC02                          (0x2UL<<4)
#define AON_LRADC_MKV0_KEY_SRC_LRADC03                          (0x3UL<<4)
#define AON_LRADC_MKV0_KEY_SRC_LRADC04                          (0x4UL<<4)
#define AON_LRADC_MKV0_KEY_SRC_LRADC05                          (0x5UL<<4)
#define AON_LRADC_MKV0_KEY_SRC_LRADC06                          (0x6UL<<4)
#define AON_LRADC_MKV0_KEY_SRC_LRADC07                          (0x7UL<<4)
#define AON_LRADC_MKV0_KEY_SRC_LRADC08                          (0x8UL<<4)
#define AON_LRADC_MKV0_KEY_SRC_LRADC09                          (0x9UL<<4)
#define AON_LRADC_MKV0_KEY_SRC_LRADC10                          (0xaUL<<4)
#define AON_LRADC_MKV0_KEY_SRC_LRADC11                          (0xbUL<<4)
#define AON_LRADC_MKV0_KEY_SRC_MASK                             (0xfUL<<4)
#define AON_LRADC_MKV0_DEB_TIME_4MS                             (0x0UL<<2)
#define AON_LRADC_MKV0_DEB_TIME_8MS                             (0x1UL<<2)
#define AON_LRADC_MKV0_DEB_TIME_16MS                            (0x2UL<<2)
#define AON_LRADC_MKV0_DEB_TIME_32MS                            (0x3UL<<2)
#define AON_LRADC_MKV0_DEB_TIME_MASK                            (0x3UL<<2)
#define AON_LRADC_MKV0_DEB_EN                                   (0x1UL<<1)
#define AON_LRADC_MKV0_KEY_EN                                   (0x1UL<<0)
/****LRADC_MKV0 end****/


/***********************************LRADC_MKV1***********************************/
#define AON_LRADC_MKV1_KEY_THD4_MASK                            (0x3ffUL<<20)
#define AON_LRADC_MKV1_KEY_THD3_MASK                            (0x3ffUL<<10)
#define AON_LRADC_MKV1_KEY_THD2_MASK                            (0x3ffUL<<0)
/****LRADC_MKV1 end****/


/***********************************LRADC_MKV2***********************************/
#define AON_LRADC_MKV2_MVK5_EDGE_NONE                           (0x0UL<<20)
#define AON_LRADC_MKV2_MVK5_EDGE_RISE                           (0x1UL<<20)
#define AON_LRADC_MKV2_MVK5_EDGE_FALL                           (0x2UL<<20)
#define AON_LRADC_MKV2_MVK5_EDGE_BOTHEDGE                       (0x3UL<<20)
#define AON_LRADC_MKV2_MVK5_EDGE_HIGH                           (0x4UL<<20)
#define AON_LRADC_MKV2_MVK5_EDGE_LOW                            (0x5UL<<20)
#define AON_LRADC_MKV2_MVK5_EDGE_MASK                           (0x7UL<<20)
#define AON_LRADC_MKV2_MVK4_EDGE_NONE                           (0x0UL<<16)
#define AON_LRADC_MKV2_MVK4_EDGE_RISE                           (0x1UL<<16)
#define AON_LRADC_MKV2_MVK4_EDGE_FALL                           (0x2UL<<16)
#define AON_LRADC_MKV2_MVK4_EDGE_BOTHEDGE                       (0x3UL<<16)
#define AON_LRADC_MKV2_MVK4_EDGE_HIGH                           (0x4UL<<16)
#define AON_LRADC_MKV2_MVK4_EDGE_LOW                            (0x5UL<<16)
#define AON_LRADC_MKV2_MVK4_EDGE_MASK                           (0x7UL<<16)
#define AON_LRADC_MKV2_MVK3_EDGE_NONE                           (0x0UL<<12)
#define AON_LRADC_MKV2_MVK3_EDGE_RISE                           (0x1UL<<12)
#define AON_LRADC_MKV2_MVK3_EDGE_FALL                           (0x2UL<<12)
#define AON_LRADC_MKV2_MVK3_EDGE_BOTHEDGE                       (0x3UL<<12)
#define AON_LRADC_MKV2_MVK3_EDGE_HIGH                           (0x4UL<<12)
#define AON_LRADC_MKV2_MVK3_EDGE_LOW                            (0x5UL<<12)
#define AON_LRADC_MKV2_MVK3_EDGE_MASK                           (0x7UL<<12)
#define AON_LRADC_MKV2_MVK2_EDGE_NONE                           (0x0UL<<8)
#define AON_LRADC_MKV2_MVK2_EDGE_RISE                           (0x1UL<<8)
#define AON_LRADC_MKV2_MVK2_EDGE_FALL                           (0x2UL<<8)
#define AON_LRADC_MKV2_MVK2_EDGE_BOTHEDGE                       (0x3UL<<8)
#define AON_LRADC_MKV2_MVK2_EDGE_HIGH                           (0x4UL<<8)
#define AON_LRADC_MKV2_MVK2_EDGE_LOW                            (0x5UL<<8)
#define AON_LRADC_MKV2_MVK2_EDGE_MASK                           (0x7UL<<8)
#define AON_LRADC_MKV2_MVK1_EDGE_NONE                           (0x0UL<<4)
#define AON_LRADC_MKV2_MVK1_EDGE_RISE                           (0x1UL<<4)
#define AON_LRADC_MKV2_MVK1_EDGE_FALL                           (0x2UL<<4)
#define AON_LRADC_MKV2_MVK1_EDGE_BOTHEDGE                       (0x3UL<<4)
#define AON_LRADC_MKV2_MVK1_EDGE_HIGH                           (0x4UL<<4)
#define AON_LRADC_MKV2_MVK1_EDGE_LOW                            (0x5UL<<4)
#define AON_LRADC_MKV2_MVK1_EDGE_MASK                           (0x7UL<<4)
#define AON_LRADC_MKV2_MVK0_EDGE_NONE                           (0x0UL<<0)
#define AON_LRADC_MKV2_MVK0_EDGE_RISE                           (0x1UL<<0)
#define AON_LRADC_MKV2_MVK0_EDGE_FALL                           (0x2UL<<0)
#define AON_LRADC_MKV2_MVK0_EDGE_BOTHEDGE                       (0x3UL<<0)
#define AON_LRADC_MKV2_MVK0_EDGE_HIGH                           (0x4UL<<0)
#define AON_LRADC_MKV2_MVK0_EDGE_LOW                            (0x5UL<<0)
#define AON_LRADC_MKV2_MVK0_EDGE_MASK                           (0x7UL<<0)
/****LRADC_MKV2 end****/


/***********************************LRADC_CTL***********************************/
#define AON_LRADC_CTL_LRADC_SELM_TIMEBASE                       (0x0UL<<8)
#define AON_LRADC_CTL_LRADC_SELM_CHANNELBASE                    (0x1UL<<8)
#define AON_LRADC_CTL_LRADC_SELM_MASK                           (0x1UL<<8)
#define AON_LRADC_CTL_FRADC_CHN_LRADC11                         (0x0UL<<4)
#define AON_LRADC_CTL_FRADC_CHN_LRADC10                         (0x1UL<<4)
#define AON_LRADC_CTL_FRADC_CHN_LRADC09                         (0x2UL<<4)
#define AON_LRADC_CTL_FRADC_CHN_LRADC08                         (0x3UL<<4)
#define AON_LRADC_CTL_FRADC_CHN_LRADC07                         (0x4UL<<4)
#define AON_LRADC_CTL_FRADC_CHN_LRADC06                         (0x5UL<<4)
#define AON_LRADC_CTL_FRADC_CHN_LRADC05                         (0x6UL<<4)
#define AON_LRADC_CTL_FRADC_CHN_LRADC04                         (0x7UL<<4)
#define AON_LRADC_CTL_FRADC_CHN_LRADC03                         (0x8UL<<4)
#define AON_LRADC_CTL_FRADC_CHN_LRADC02                         (0x9UL<<4)
#define AON_LRADC_CTL_FRADC_CHN_LRADC01                         (0xaUL<<4)
#define AON_LRADC_CTL_FRADC_CHN_LRADC00                         (0xbUL<<4)
#define AON_LRADC_CTL_FRADC_CHN_MASK                            (0xfUL<<4)
#define AON_LRADC_CTL_LRADC_NUM_32                              (0x0UL<<1)
#define AON_LRADC_CTL_LRADC_NUM_16                              (0x1UL<<1)
#define AON_LRADC_CTL_LRADC_NUM_8                               (0x2UL<<1)
#define AON_LRADC_CTL_LRADC_NUM_4                               (0x3UL<<1)
#define AON_LRADC_CTL_LRADC_NUM_2                               (0x4UL<<1)
#define AON_LRADC_CTL_LRADC_NUM_MASK                            (0x7UL<<1)
#define AON_LRADC_CTL_EN                                        (0x1UL<<0)
/****LRADC_CTL end****/


/***********************************LRADC_IE***********************************/
#define AON_LRADC_IE_LRADC_MVK5_IE                              (0x1UL<<29)
#define AON_LRADC_IE_LRADC_MVK4_IE                              (0x1UL<<28)
#define AON_LRADC_IE_LRADC_MVK3_IE                              (0x1UL<<27)
#define AON_LRADC_IE_LRADC_MVK2_IE                              (0x1UL<<26)
#define AON_LRADC_IE_LRADC_MVK1_IE                              (0x1UL<<25)
#define AON_LRADC_IE_LRADC_MVK0_IE                              (0x1UL<<24)
#define AON_LRADC_IE_LRADC11_SVK_IE                             (0x1UL<<23)
#define AON_LRADC_IE_LRADC10_SVK_IE                             (0x1UL<<22)
#define AON_LRADC_IE_LRADC09_SVK_IE                             (0x1UL<<21)
#define AON_LRADC_IE_LRADC08_SVK_IE                             (0x1UL<<20)
#define AON_LRADC_IE_LRADC07_SVK_IE                             (0x1UL<<19)
#define AON_LRADC_IE_LRADC06_SVK_IE                             (0x1UL<<18)
#define AON_LRADC_IE_LRADC05_SVK_IE                             (0x1UL<<17)
#define AON_LRADC_IE_LRADC04_SVK_IE                             (0x1UL<<16)
#define AON_LRADC_IE_LRADC03_SVK_IE                             (0x1UL<<15)
#define AON_LRADC_IE_LRADC02_SVK_IE                             (0x1UL<<14)
#define AON_LRADC_IE_LRADC01_SVK_IE                             (0x1UL<<13)
#define AON_LRADC_IE_LRADC00_SVK_IE                             (0x1UL<<12)
#define AON_LRADC_IE_LRADC11_END_IE                             (0x1UL<<11)
#define AON_LRADC_IE_LRADC10_END_IE                             (0x1UL<<10)
#define AON_LRADC_IE_LRADC09_END_IE                             (0x1UL<<9)
#define AON_LRADC_IE_LRADC08_END_IE                             (0x1UL<<8)
#define AON_LRADC_IE_LRADC07_END_IE                             (0x1UL<<7)
#define AON_LRADC_IE_LRADC06_END_IE                             (0x1UL<<6)
#define AON_LRADC_IE_LRADC05_END_IE                             (0x1UL<<5)
#define AON_LRADC_IE_LRADC04_END_IE                             (0x1UL<<4)
#define AON_LRADC_IE_LRADC03_END_IE                             (0x1UL<<3)
#define AON_LRADC_IE_LRADC02_END_IE                             (0x1UL<<2)
#define AON_LRADC_IE_LRADC01_END_IE                             (0x1UL<<1)
#define AON_LRADC_IE_LRADC00_END_IE                             (0x1UL<<0)
/****LRADC_IE end****/


/***********************************LRADC_WKEN***********************************/
#define AON_LRADC_WKEN_LRADC_MVK5_WKEN                          (0x1UL<<29)
#define AON_LRADC_WKEN_LRADC_MVK4_WKEN                          (0x1UL<<28)
#define AON_LRADC_WKEN_LRADC_MVK3_WKEN                          (0x1UL<<27)
#define AON_LRADC_WKEN_LRADC_MVK2_WKEN                          (0x1UL<<26)
#define AON_LRADC_WKEN_LRADC_MVK1_WKEN                          (0x1UL<<25)
#define AON_LRADC_WKEN_LRADC_MVK0_WKEN                          (0x1UL<<24)
#define AON_LRADC_WKEN_LRADC11_SVK_WKEN                         (0x1UL<<23)
#define AON_LRADC_WKEN_LRADC10_SVK_WKEN                         (0x1UL<<22)
#define AON_LRADC_WKEN_LRADC09_SVK_WKEN                         (0x1UL<<21)
#define AON_LRADC_WKEN_LRADC08_SVK_WKEN                         (0x1UL<<20)
#define AON_LRADC_WKEN_LRADC07_SVK_WKEN                         (0x1UL<<19)
#define AON_LRADC_WKEN_LRADC06_SVK_WKEN                         (0x1UL<<18)
#define AON_LRADC_WKEN_LRADC05_SVK_WKEN                         (0x1UL<<17)
#define AON_LRADC_WKEN_LRADC04_SVK_WKEN                         (0x1UL<<16)
#define AON_LRADC_WKEN_LRADC03_SVK_WKEN                         (0x1UL<<15)
#define AON_LRADC_WKEN_LRADC02_SVK_WKEN                         (0x1UL<<14)
#define AON_LRADC_WKEN_LRADC01_SVK_WKEN                         (0x1UL<<13)
#define AON_LRADC_WKEN_LRADC00_SVK_WKEN                         (0x1UL<<12)
#define AON_LRADC_WKEN_LRADC11_END_WKEN                         (0x1UL<<11)
#define AON_LRADC_WKEN_LRADC10_END_WKEN                         (0x1UL<<10)
#define AON_LRADC_WKEN_LRADC09_END_WKEN                         (0x1UL<<9)
#define AON_LRADC_WKEN_LRADC08_END_WKEN                         (0x1UL<<8)
#define AON_LRADC_WKEN_LRADC07_END_WKEN                         (0x1UL<<7)
#define AON_LRADC_WKEN_LRADC06_END_WKEN                         (0x1UL<<6)
#define AON_LRADC_WKEN_LRADC05_END_WKEN                         (0x1UL<<5)
#define AON_LRADC_WKEN_LRADC04_END_WKEN                         (0x1UL<<4)
#define AON_LRADC_WKEN_LRADC03_END_WKEN                         (0x1UL<<3)
#define AON_LRADC_WKEN_LRADC02_END_WKEN                         (0x1UL<<2)
#define AON_LRADC_WKEN_LRADC01_END_WKEN                         (0x1UL<<1)
#define AON_LRADC_WKEN_LRADC00_END_WKEN                         (0x1UL<<0)
/****LRADC_WKEN end****/


/***********************************LRADC_PD***********************************/
#define AON_LRADC_PD_LRADC_MVK5_PD                              (0x1UL<<29)
#define AON_LRADC_PD_LRADC_MVK4_PD                              (0x1UL<<28)
#define AON_LRADC_PD_LRADC_MVK3_PD                              (0x1UL<<27)
#define AON_LRADC_PD_LRADC_MVK2_PD                              (0x1UL<<26)
#define AON_LRADC_PD_LRADC_MVK1_PD                              (0x1UL<<25)
#define AON_LRADC_PD_LRADC_MVK0_PD                              (0x1UL<<24)
#define AON_LRADC_PD_LRADC11_SVK_PD                             (0x1UL<<23)
#define AON_LRADC_PD_LRADC10_SVK_PD                             (0x1UL<<22)
#define AON_LRADC_PD_LRADC09_SVK_PD                             (0x1UL<<21)
#define AON_LRADC_PD_LRADC08_SVK_PD                             (0x1UL<<20)
#define AON_LRADC_PD_LRADC07_SVK_PD                             (0x1UL<<19)
#define AON_LRADC_PD_LRADC06_SVK_PD                             (0x1UL<<18)
#define AON_LRADC_PD_LRADC05_SVK_PD                             (0x1UL<<17)
#define AON_LRADC_PD_LRADC04_SVK_PD                             (0x1UL<<16)
#define AON_LRADC_PD_LRADC03_SVK_PD                             (0x1UL<<15)
#define AON_LRADC_PD_LRADC02_SVK_PD                             (0x1UL<<14)
#define AON_LRADC_PD_LRADC01_SVK_PD                             (0x1UL<<13)
#define AON_LRADC_PD_LRADC00_SVK_PD                             (0x1UL<<12)
#define AON_LRADC_PD_LRADC11_END_PD                             (0x1UL<<11)
#define AON_LRADC_PD_LRADC10_END_PD                             (0x1UL<<10)
#define AON_LRADC_PD_LRADC09_END_PD                             (0x1UL<<9)
#define AON_LRADC_PD_LRADC08_END_PD                             (0x1UL<<8)
#define AON_LRADC_PD_LRADC07_END_PD                             (0x1UL<<7)
#define AON_LRADC_PD_LRADC06_END_PD                             (0x1UL<<6)
#define AON_LRADC_PD_LRADC05_END_PD                             (0x1UL<<5)
#define AON_LRADC_PD_LRADC04_END_PD                             (0x1UL<<4)
#define AON_LRADC_PD_LRADC03_END_PD                             (0x1UL<<3)
#define AON_LRADC_PD_LRADC02_END_PD                             (0x1UL<<2)
#define AON_LRADC_PD_LRADC01_END_PD                             (0x1UL<<1)
#define AON_LRADC_PD_LRADC00_END_PD                             (0x1UL<<0)
/****LRADC_PD end****/


/***********************************LRADC_DATn***********************************/
#define AON_LRADC_DATn_DATA_MASK                                (0x3ffUL<<0)
/****LRADC_DATn end****/


/***********************************LRADC_KEYD***********************************/
#define AON_LRADC_KEYD_LRADC_MVK5                               (0x1UL<<17)
#define AON_LRADC_KEYD_LRADC_MVK4                               (0x1UL<<16)
#define AON_LRADC_KEYD_LRADC_MVK3                               (0x1UL<<15)
#define AON_LRADC_KEYD_LRADC_MVK2                               (0x1UL<<14)
#define AON_LRADC_KEYD_LRADC_MVK1                               (0x1UL<<13)
#define AON_LRADC_KEYD_LRADC_MVK0                               (0x1UL<<12)
#define AON_LRADC_KEYD_LRADC11_SVK                              (0x1UL<<11)
#define AON_LRADC_KEYD_LRADC10_SVK                              (0x1UL<<10)
#define AON_LRADC_KEYD_LRADC09_SVK                              (0x1UL<<9)
#define AON_LRADC_KEYD_LRADC08_SVK                              (0x1UL<<8)
#define AON_LRADC_KEYD_LRADC07_SVK                              (0x1UL<<7)
#define AON_LRADC_KEYD_LRADC06_SVK                              (0x1UL<<6)
#define AON_LRADC_KEYD_LRADC05_SVK                              (0x1UL<<5)
#define AON_LRADC_KEYD_LRADC04_SVK                              (0x1UL<<4)
#define AON_LRADC_KEYD_LRADC03_SVK                              (0x1UL<<3)
#define AON_LRADC_KEYD_LRADC02_SVK                              (0x1UL<<2)
#define AON_LRADC_KEYD_LRADC01_SVK                              (0x1UL<<1)
#define AON_LRADC_KEYD_LRADC00_SVK                              (0x1UL<<0)
/****LRADC_KEYD end****/


/***********************************AON_LRADC register***********************************/
typedef struct
{
    __IO    uint32_t    CFGn[12];                                /* 0x0    LRADC Channel 00 Configuration */
    __IO    uint32_t    ANA;                                     /* 0x30    LRADC Analog Control */
    __IO    uint32_t    MKV0;                                    /* 0x34    LRADC Key Control0 */
    __IO    uint32_t    MKV1;                                    /* 0x38    LRADC Key Control1 */
    __IO    uint32_t    MKV2;                                    /* 0x3c    LRADC Key Control2 */
    __IO    uint32_t    CTL;                                     /* 0x40    LRADC Control */
    __IO    uint32_t    IE;                                      /* 0x44    LRADC Interrupt Enable */
    __IO    uint32_t    WKEN;                                    /* 0x48    LRADC Wakeup Enable */
    __IO    uint32_t    PD;                                      /* 0x4c    LRADC Interrupt Pending */
    __IO    uint32_t    DATn[12];                                /* 0x50    LRADC Channel 00 Out */
    __I     uint32_t    KEYD;                                    /* 0x80    LRADC Key Data */
} AON_LRADC_RegDef;
/****AON_LRADC end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
