#ifndef __DEV_ADC_H__
#define __DEV_ADC_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************ADC_CHNn_CFG***********************************/
#define DEV_ADC_CHNn_CFG_MIX_GAIN_1                             (0x0UL<<30)
#define DEV_ADC_CHNn_CFG_MIX_GAIN_1_2                           (0x1UL<<30)
#define DEV_ADC_CHNn_CFG_MIX_GAIN_MASK                          (0x1UL<<30)
#define DEV_ADC_CHNn_CFG_MIX_SRC_SEL_DISABLE                    (0x0UL<<28)
#define DEV_ADC_CHNn_CFG_MIX_SRC_SEL_ENABLE                     (0x1UL<<28)
#define DEV_ADC_CHNn_CFG_MIX_SRC_SEL_MASK                       (0x3UL<<28)
#define DEV_ADC_CHNn_CFG_DMIC_PIN_SEL_CHN0_1MIXCHN2_3MIX        (0x0UL<<27)
#define DEV_ADC_CHNn_CFG_DMIC_PIN_SEL_INDIVIDUAL                (0x1UL<<27)
#define DEV_ADC_CHNn_CFG_DMIC_PIN_SEL_MASK                      (0x1UL<<27)
#define DEV_ADC_CHNn_CFG_DMIC_CLK_DIV_2                         (0x0UL<<24)
#define DEV_ADC_CHNn_CFG_DMIC_CLK_DIV_4                         (0x1UL<<24)
#define DEV_ADC_CHNn_CFG_DMIC_CLK_DIV_6                         (0x2UL<<24)
#define DEV_ADC_CHNn_CFG_DMIC_CLK_DIV_8                         (0x3UL<<24)
#define DEV_ADC_CHNn_CFG_DMIC_CLK_DIV_12                        (0x4UL<<24)
#define DEV_ADC_CHNn_CFG_DMIC_CLK_DIV_16                        (0x5UL<<24)
#define DEV_ADC_CHNn_CFG_DMIC_CLK_DIV_MASK                      (0x7UL<<24)
#define DEV_ADC_CHNn_CFG_DMIC_DLY_SEL_NODELAY                   (0x0UL<<22)
#define DEV_ADC_CHNn_CFG_DMIC_DLY_SEL_1CYCLESOF24MHOSC          (0x1UL<<22)
#define DEV_ADC_CHNn_CFG_DMIC_DLY_SEL_2CYCLESOF24MHOSC          (0x2UL<<22)
#define DEV_ADC_CHNn_CFG_DMIC_DLY_SEL_3CYCLESOF24MHOSC          (0x3UL<<22)
#define DEV_ADC_CHNn_CFG_DMIC_DLY_SEL_MASK                      (0x3UL<<22)
#define DEV_ADC_CHNn_CFG_CIC_CLK_PHASE_POSITIVE                 (0x0UL<<21)
#define DEV_ADC_CHNn_CFG_CIC_CLK_PHASE_NEGTIVE                  (0x1UL<<21)
#define DEV_ADC_CHNn_CFG_CIC_CLK_PHASE_MASK                     (0x1UL<<21)
#define DEV_ADC_CHNn_CFG_HPF_COEF_1_16                          (0x0UL<<17)
#define DEV_ADC_CHNn_CFG_HPF_COEF_1_32                          (0x1UL<<17)
#define DEV_ADC_CHNn_CFG_HPF_COEF_1_64                          (0x2UL<<17)
#define DEV_ADC_CHNn_CFG_HPF_COEF_1_128                         (0x3UL<<17)
#define DEV_ADC_CHNn_CFG_HPF_COEF_1_256                         (0x4UL<<17)
#define DEV_ADC_CHNn_CFG_HPF_COEF_1_512                         (0x5UL<<17)
#define DEV_ADC_CHNn_CFG_HPF_COEF_1_1024                        (0x6UL<<17)
#define DEV_ADC_CHNn_CFG_HPF_COEF_1_2048                        (0x7UL<<17)
#define DEV_ADC_CHNn_CFG_HPF_COEF_MASK                          (0x7UL<<17)
#define DEV_ADC_CHNn_CFG_HPF_EN_DISABLE                         (0x0UL<<16)
#define DEV_ADC_CHNn_CFG_HPF_EN_ENABLE                          (0x1UL<<16)
#define DEV_ADC_CHNn_CFG_HPF_EN_MASK                            (0x1UL<<16)
#define DEV_ADC_CHNn_CFG_VOL_16X                                (0x0UL<<12)
#define DEV_ADC_CHNn_CFG_VOL_8X                                 (0x1UL<<12)
#define DEV_ADC_CHNn_CFG_VOL_4X                                 (0x2UL<<12)
#define DEV_ADC_CHNn_CFG_VOL_2X                                 (0x3UL<<12)
#define DEV_ADC_CHNn_CFG_VOL_1X                                 (0x4UL<<12)
#define DEV_ADC_CHNn_CFG_VOL_1_2X                               (0x5UL<<12)
#define DEV_ADC_CHNn_CFG_VOL_1_4X                               (0x6UL<<12)
#define DEV_ADC_CHNn_CFG_VOL_1_8X                               (0x7UL<<12)
#define DEV_ADC_CHNn_CFG_VOL_1_16X                              (0x8UL<<12)
#define DEV_ADC_CHNn_CFG_VOL_MASK                               (0xfUL<<12)
#define DEV_ADC_CHNn_CFG_FIR_CLK_DIV_1                          (0x0UL<<9)
#define DEV_ADC_CHNn_CFG_FIR_CLK_DIV_2                          (0x1UL<<9)
#define DEV_ADC_CHNn_CFG_FIR_CLK_DIV_4                          (0x2UL<<9)
#define DEV_ADC_CHNn_CFG_FIR_CLK_DIV_6                          (0x3UL<<9)
#define DEV_ADC_CHNn_CFG_FIR_CLK_DIV_8                          (0x4UL<<9)
#define DEV_ADC_CHNn_CFG_FIR_CLK_DIV_12                         (0x5UL<<9)
#define DEV_ADC_CHNn_CFG_FIR_CLK_DIV_16                         (0x6UL<<9)
#define DEV_ADC_CHNn_CFG_FIR_CLK_DIV_24                         (0x7UL<<9)
#define DEV_ADC_CHNn_CFG_FIR_CLK_DIV_MASK                       (0x7UL<<9)
#define DEV_ADC_CHNn_CFG_FIR_CLK_SEL_DEBUGINCLOCK               (0x0UL<<8)
#define DEV_ADC_CHNn_CFG_FIR_CLK_SEL_DACCLOCK                   (0x1UL<<8)
#define DEV_ADC_CHNn_CFG_FIR_CLK_SEL_MASK                       (0x1UL<<8)
#define DEV_ADC_CHNn_CFG_CIC_CLK_DIV_256FS_2_128FS              (0x0UL<<6)
#define DEV_ADC_CHNn_CFG_CIC_CLK_DIV_256FS_4__64FS              (0x1UL<<6)
#define DEV_ADC_CHNn_CFG_CIC_CLK_DIV_256FS_8__32FS              (0x2UL<<6)
#define DEV_ADC_CHNn_CFG_CIC_CLK_DIV_MASK                       (0x3UL<<6)
#define DEV_ADC_CHNn_CFG_CIC_DAT_SEL_DEBUGINDATA                (0x0UL<<5)
#define DEV_ADC_CHNn_CFG_CIC_DAT_SEL_DACSDMDATA                 (0x1UL<<5)
#define DEV_ADC_CHNn_CFG_CIC_DAT_SEL_MASK                       (0x1UL<<5)
#define DEV_ADC_CHNn_CFG_CIC_CLK_SEL_DEBUGINCLOCK               (0x0UL<<4)
#define DEV_ADC_CHNn_CFG_CIC_CLK_SEL_DACCLOCK                   (0x1UL<<4)
#define DEV_ADC_CHNn_CFG_CIC_CLK_SEL_MASK                       (0x1UL<<4)
#define DEV_ADC_CHNn_CFG_CIC_SEL_32XDECIMATION                  (0x0UL<<2)
#define DEV_ADC_CHNn_CFG_CIC_SEL_16XDECIMATION                  (0x1UL<<2)
#define DEV_ADC_CHNn_CFG_CIC_SEL_08XDECIMATION                  (0x2UL<<2)
#define DEV_ADC_CHNn_CFG_CIC_SEL_04XDECIMATION                  (0x3UL<<2)
#define DEV_ADC_CHNn_CFG_CIC_SEL_MASK                           (0x3UL<<2)
#define DEV_ADC_CHNn_CFG_MODE_SEL_ADC                           (0x0UL<<1)
#define DEV_ADC_CHNn_CFG_MODE_SEL_DMIC                          (0x1UL<<1)
#define DEV_ADC_CHNn_CFG_MODE_SEL_MASK                          (0x1UL<<1)
#define DEV_ADC_CHNn_CFG_CHN_EN_DISABLE                         (0x0UL<<0)
#define DEV_ADC_CHNn_CFG_CHN_EN_ENABLE                          (0x1UL<<0)
#define DEV_ADC_CHNn_CFG_CHN_EN_MASK                            (0x1UL<<0)
/****ADC_CHNn_CFG end****/


/***********************************ADC_CFG***********************************/
#define DEV_ADC_CFG_FIFO_DAT_SEL_DISABLE                        (0x0UL<<24)
#define DEV_ADC_CFG_FIFO_DAT_SEL_ENABLE                         (0x1UL<<24)
#define DEV_ADC_CFG_FIFO_DAT_SEL_CHANNEL0                       (0x18UL<<24)
#define DEV_ADC_CFG_FIFO_DAT_SEL_CHANNEL1                       (0x19UL<<24)
#define DEV_ADC_CFG_FIFO_DAT_SEL_CHANNEL2                       (0x1aUL<<24)
#define DEV_ADC_CFG_FIFO_DAT_SEL_CHANNEL3                       (0x1bUL<<24)
#define DEV_ADC_CFG_FIFO_DAT_SEL_MASK                           (0xfUL<<24)
#define DEV_ADC_CFG_FIFO_CLK_SEL_CHANNEL0CLOCK                  (0x0UL<<20)
#define DEV_ADC_CFG_FIFO_CLK_SEL_CHANNEL1CLOCK                  (0x1UL<<20)
#define DEV_ADC_CFG_FIFO_CLK_SEL_CHANNEL2CLOCK                  (0x2UL<<20)
#define DEV_ADC_CFG_FIFO_CLK_SEL_CHANNEL3CLOCK                  (0x3UL<<20)
#define DEV_ADC_CFG_FIFO_CLK_SEL_MASK                           (0x3UL<<20)
#define DEV_ADC_CFG_DBG_CHN_SEL_CHANNEL0                        (0x0UL<<18)
#define DEV_ADC_CFG_DBG_CHN_SEL_CHANNEL1                        (0x1UL<<18)
#define DEV_ADC_CFG_DBG_CHN_SEL_CHANNEL2                        (0x2UL<<18)
#define DEV_ADC_CFG_DBG_CHN_SEL_CHANNEL3                        (0x3UL<<18)
#define DEV_ADC_CFG_DBG_CHN_SEL_MASK                            (0x3UL<<18)
#define DEV_ADC_CFG_DBG_OUT_EN_DISABLE                          (0x0UL<<17)
#define DEV_ADC_CFG_DBG_OUT_EN_ENABLE                           (0x1UL<<17)
#define DEV_ADC_CFG_DBG_OUT_EN_MASK                             (0x1UL<<17)
#define DEV_ADC_CFG_DBG_IN_EN_DISABLE                           (0x0UL<<16)
#define DEV_ADC_CFG_DBG_IN_EN_ENABLE                            (0x1UL<<16)
#define DEV_ADC_CFG_DBG_IN_EN_MASK                              (0x1UL<<16)
#define DEV_ADC_CFG_HFUL_TH_MASK                                (0x3fUL<<8)
#define DEV_ADC_CFG_ADC_WIDTH_24BIT                             (0x0UL<<6)
#define DEV_ADC_CFG_ADC_WIDTH_16BIT                             (0x1UL<<6)
#define DEV_ADC_CFG_ADC_WIDTH_MASK                              (0x1UL<<6)
/****ADC_CFG end****/


/***********************************ADC_CTL***********************************/
#define DEV_ADC_CTL_RX_FIFO_RST_RXFIFOWORK                      (0x0UL<<3)
#define DEV_ADC_CTL_RX_FIFO_RST_RXFIFORESET                     (0x1UL<<3)
#define DEV_ADC_CTL_RX_FIFO_RST_MASK                            (0x1UL<<3)
#define DEV_ADC_CTL_SRC_SEL_AHBINTERFACE                        (0x0UL<<2)
#define DEV_ADC_CTL_SRC_SEL_SRCINTERFACE                        (0x1UL<<2)
#define DEV_ADC_CTL_SRC_SEL_MASK                                (0x1UL<<2)
#define DEV_ADC_CTL_DMA_EN_DISABLE                              (0x0UL<<1)
#define DEV_ADC_CTL_DMA_EN_ENABLE                               (0x1UL<<1)
#define DEV_ADC_CTL_DMA_EN_MASK                                 (0x1UL<<1)
#define DEV_ADC_CTL_ADC_EN_DISABLE                              (0x0UL<<0)
#define DEV_ADC_CTL_ADC_EN_ENABLE                               (0x1UL<<0)
#define DEV_ADC_CTL_ADC_EN_MASK                                 (0x1UL<<0)
/****ADC_CTL end****/


/***********************************ADC_IE***********************************/
#define DEV_ADC_IE_RX_FIFO_UF                                   (0x1UL<<2)
#define DEV_ADC_IE_RX_FIFO_OF                                   (0x1UL<<1)
#define DEV_ADC_IE_RX_IRQ                                       (0x1UL<<0)
/****ADC_IE end****/


/***********************************ADC_PD***********************************/
#define DEV_ADC_PD_RX_FIFO_UF                                   (0x1UL<<2)
#define DEV_ADC_PD_RX_FIFO_OF                                   (0x1UL<<1)
#define DEV_ADC_PD_RX_IRQ                                       (0x1UL<<0)
/****ADC_PD end****/


/***********************************ADC_STA***********************************/
#define DEV_ADC_STA_RX_FIFO_FULL                                (0x1UL<<11)
#define DEV_ADC_STA_RX_FIFO_HFUL                                (0x1UL<<10)
#define DEV_ADC_STA_RX_FIFO_EMPT                                (0x1UL<<9)
#define DEV_ADC_STA_RX_FIFO_HEMP                                (0x1UL<<8)
#define DEV_ADC_STA_RX_FIFO_RLVL_MASK                           (0x3fUL<<0)
/****ADC_STA end****/


/***********************************ADC_RBUF***********************************/
#define DEV_ADC_RBUF_MASK                                       (0xffffffUL<<8)
/****ADC_RBUF end****/


/***********************************ADC_GAIN_CFG***********************************/
#define DEV_ADC_GAIN_CFG_Target_level_0DB                       (0x0UL<<24)
#define DEV_ADC_GAIN_CFG_Target_level_1DB                       (0x1UL<<24)
#define DEV_ADC_GAIN_CFG_Target_level_2DB                       (0x2UL<<24)
#define DEV_ADC_GAIN_CFG_Target_level_MASK                      (0xffUL<<24)
#define DEV_ADC_GAIN_CFG_Noise_level_0DB                        (0x0UL<<16)
#define DEV_ADC_GAIN_CFG_Noise_level_1DB                        (0x1UL<<16)
#define DEV_ADC_GAIN_CFG_Noise_level_2DB                        (0x2UL<<16)
#define DEV_ADC_GAIN_CFG_Noise_level_MASK                       (0xffUL<<16)
#define DEV_ADC_GAIN_CFG_Max_gain_0DB                           (0x0UL<<8)
#define DEV_ADC_GAIN_CFG_Max_gain_1DB                           (0x1UL<<8)
#define DEV_ADC_GAIN_CFG_Max_gain_2DB                           (0x2UL<<8)
#define DEV_ADC_GAIN_CFG_Max_gain_MASK                          (0xfUL<<8)
#define DEV_ADC_GAIN_CFG_Min_gain_0DB                           (0x0UL<<4)
#define DEV_ADC_GAIN_CFG_Min_gain_1DB                           (0x1UL<<4)
#define DEV_ADC_GAIN_CFG_Min_gain_2DB                           (0x2UL<<4)
#define DEV_ADC_GAIN_CFG_Min_gain_MASK                          (0xfUL<<4)
#define DEV_ADC_GAIN_CFG_Hysteresis_0DB                         (0x0UL<<2)
#define DEV_ADC_GAIN_CFG_Hysteresis_1DB                         (0x1UL<<2)
#define DEV_ADC_GAIN_CFG_Hysteresis_2DB                         (0x2UL<<2)
#define DEV_ADC_GAIN_CFG_Hysteresis_3DB                         (0x3UL<<2)
#define DEV_ADC_GAIN_CFG_Hysteresis_MASK                        (0x3UL<<2)
#define DEV_ADC_GAIN_CFG_NOISE_GATE_EN_DISABLE                  (0x0UL<<1)
#define DEV_ADC_GAIN_CFG_NOISE_GATE_EN_ENABLE                   (0x1UL<<1)
#define DEV_ADC_GAIN_CFG_NOISE_GATE_EN_MASK                     (0x1UL<<1)
#define DEV_ADC_GAIN_CFG_AGC_EN_DISABLE                         (0x0UL<<0)
#define DEV_ADC_GAIN_CFG_AGC_EN_ENABLE                          (0x1UL<<0)
#define DEV_ADC_GAIN_CFG_AGC_EN_MASK                            (0x1UL<<0)
/****ADC_GAIN_CFG end****/


/***********************************ADC_PEAK_AT***********************************/
#define DEV_ADC_PEAK_AT_ATTACK_TIME_MASK                        (0xffffffffUL<<0)
/****ADC_PEAK_AT end****/


/***********************************ADC_PEAK_RT***********************************/
#define DEV_ADC_PEAK_RT_RELEASE_TIME_MASK                       (0xffffffffUL<<0)
/****ADC_PEAK_RT end****/


/***********************************ADC_GAIN_AT***********************************/
#define DEV_ADC_GAIN_AT_ATTACK_TIME_MASK                        (0xffffffffUL<<0)
/****ADC_GAIN_AT end****/


/***********************************ADC_GAIN_RT***********************************/
#define DEV_ADC_GAIN_RT_RELEASE_TIME_MASK                       (0xffffffffUL<<0)
/****ADC_GAIN_RT end****/


/***********************************ADC_BIST_EN***********************************/
#define DEV_ADC_BIST_EN_CHN3_BIST_LS_DISABLE                    (0x0UL<<11)
#define DEV_ADC_BIST_EN_CHN3_BIST_LS_ENABLE                     (0x1UL<<11)
#define DEV_ADC_BIST_EN_CHN3_BIST_LS_MASK                       (0x1UL<<11)
#define DEV_ADC_BIST_EN_CHN2_BIST_LS_DISABLE                    (0x0UL<<10)
#define DEV_ADC_BIST_EN_CHN2_BIST_LS_ENABLE                     (0x1UL<<10)
#define DEV_ADC_BIST_EN_CHN2_BIST_LS_MASK                       (0x1UL<<10)
#define DEV_ADC_BIST_EN_CHN1_BIST_LS_DISABLE                    (0x0UL<<9)
#define DEV_ADC_BIST_EN_CHN1_BIST_LS_ENABLE                     (0x1UL<<9)
#define DEV_ADC_BIST_EN_CHN1_BIST_LS_MASK                       (0x1UL<<9)
#define DEV_ADC_BIST_EN_CHN0_BIST_LS_DISABLE                    (0x0UL<<8)
#define DEV_ADC_BIST_EN_CHN0_BIST_LS_ENABLE                     (0x1UL<<8)
#define DEV_ADC_BIST_EN_CHN0_BIST_LS_MASK                       (0x1UL<<8)
#define DEV_ADC_BIST_EN_CHN3_BIST_RME_DISABLE                   (0x0UL<<7)
#define DEV_ADC_BIST_EN_CHN3_BIST_RME_ENABLE                    (0x1UL<<7)
#define DEV_ADC_BIST_EN_CHN3_BIST_RME_MASK                      (0x1UL<<7)
#define DEV_ADC_BIST_EN_CHN2_BIST_RME_DISABLE                   (0x0UL<<6)
#define DEV_ADC_BIST_EN_CHN2_BIST_RME_ENABLE                    (0x1UL<<6)
#define DEV_ADC_BIST_EN_CHN2_BIST_RME_MASK                      (0x1UL<<6)
#define DEV_ADC_BIST_EN_CHN1_BIST_RME_DISABLE                   (0x0UL<<5)
#define DEV_ADC_BIST_EN_CHN1_BIST_RME_ENABLE                    (0x1UL<<5)
#define DEV_ADC_BIST_EN_CHN1_BIST_RME_MASK                      (0x1UL<<5)
#define DEV_ADC_BIST_EN_CHN0_BIST_RME_DISABLE                   (0x0UL<<4)
#define DEV_ADC_BIST_EN_CHN0_BIST_RME_ENABLE                    (0x1UL<<4)
#define DEV_ADC_BIST_EN_CHN0_BIST_RME_MASK                      (0x1UL<<4)
#define DEV_ADC_BIST_EN_CHN3_BIST_EN_DISABLE                    (0x0UL<<3)
#define DEV_ADC_BIST_EN_CHN3_BIST_EN_ENABLE                     (0x1UL<<3)
#define DEV_ADC_BIST_EN_CHN3_BIST_EN_MASK                       (0x1UL<<3)
#define DEV_ADC_BIST_EN_CHN2_BIST_EN_DISABLE                    (0x0UL<<2)
#define DEV_ADC_BIST_EN_CHN2_BIST_EN_ENABLE                     (0x1UL<<2)
#define DEV_ADC_BIST_EN_CHN2_BIST_EN_MASK                       (0x1UL<<2)
#define DEV_ADC_BIST_EN_CHN1_BIST_EN_DISABLE                    (0x0UL<<1)
#define DEV_ADC_BIST_EN_CHN1_BIST_EN_ENABLE                     (0x1UL<<1)
#define DEV_ADC_BIST_EN_CHN1_BIST_EN_MASK                       (0x1UL<<1)
#define DEV_ADC_BIST_EN_CHN0_BIST_EN_DISABLE                    (0x0UL<<0)
#define DEV_ADC_BIST_EN_CHN0_BIST_EN_ENABLE                     (0x1UL<<0)
#define DEV_ADC_BIST_EN_CHN0_BIST_EN_MASK                       (0x1UL<<0)
/****ADC_BIST_EN end****/


/***********************************ADC_BIST_RM***********************************/
#define DEV_ADC_BIST_RM_CHN3_RAM_RM_MASK                        (0xfUL<<12)
#define DEV_ADC_BIST_RM_CHN2_RAM_RM_MASK                        (0xfUL<<8)
#define DEV_ADC_BIST_RM_CHN1_RAM_RM_MASK                        (0xfUL<<4)
#define DEV_ADC_BIST_RM_CHN0_RAM_RM_MASK                        (0xfUL<<0)
/****ADC_BIST_RM end****/


/***********************************ADC_BIST_DONE***********************************/
#define DEV_ADC_BIST_DONE_CHN3_RAM_DONE                         (0x1UL<<3)
#define DEV_ADC_BIST_DONE_CHN2_RAM_DONE                         (0x1UL<<2)
#define DEV_ADC_BIST_DONE_CHN1_RAM_DONE                         (0x1UL<<1)
#define DEV_ADC_BIST_DONE_CHN0_RAM_DONE                         (0x1UL<<0)
/****ADC_BIST_DONE end****/


/***********************************ADC_BIST_FAIL***********************************/
#define DEV_ADC_BIST_FAIL_CHN3_RAM_FAIL                         (0x1UL<<3)
#define DEV_ADC_BIST_FAIL_CHN2_RAM_FAIL                         (0x1UL<<2)
#define DEV_ADC_BIST_FAIL_CHN1_RAM_FAIL                         (0x1UL<<1)
#define DEV_ADC_BIST_FAIL_CHN0_RAM_FAIL                         (0x1UL<<0)
/****ADC_BIST_FAIL end****/


/***********************************ADC_MIC_CTRL0***********************************/
#define DEV_ADC_MIC_CTRL0_MIC3_GAIN_MASK                        (0x7UL<<28)
#define DEV_ADC_MIC_CTRL0_MIC3_MODE_MIC_MIX                     (0x0UL<<26)
#define DEV_ADC_MIC_CTRL0_MIC3_MODE_SINGLE_N                    (0x1UL<<26)
#define DEV_ADC_MIC_CTRL0_MIC3_MODE_SINGLE_P                    (0x2UL<<26)
#define DEV_ADC_MIC_CTRL0_MIC3_MODE_DIFFERENT                   (0x3UL<<26)
#define DEV_ADC_MIC_CTRL0_MIC3_MODE_MASK                        (0x3UL<<26)
#define DEV_ADC_MIC_CTRL0_MIC3_EN_DISABLE                       (0x0UL<<24)
#define DEV_ADC_MIC_CTRL0_MIC3_EN_ENABLE                        (0x1UL<<24)
#define DEV_ADC_MIC_CTRL0_MIC3_EN_MASK                          (0x1UL<<24)
#define DEV_ADC_MIC_CTRL0_MIC2_GAIN_MASK                        (0x7UL<<20)
#define DEV_ADC_MIC_CTRL0_MIC2_MODE_MIC_MIX                     (0x0UL<<18)
#define DEV_ADC_MIC_CTRL0_MIC2_MODE_SINGLE_N                    (0x1UL<<18)
#define DEV_ADC_MIC_CTRL0_MIC2_MODE_SINGLE_P                    (0x2UL<<18)
#define DEV_ADC_MIC_CTRL0_MIC2_MODE_DIFFERENT                   (0x3UL<<18)
#define DEV_ADC_MIC_CTRL0_MIC2_MODE_MASK                        (0x3UL<<18)
#define DEV_ADC_MIC_CTRL0_MIC2_EN_DISABLE                       (0x0UL<<16)
#define DEV_ADC_MIC_CTRL0_MIC2_EN_ENABLE                        (0x1UL<<16)
#define DEV_ADC_MIC_CTRL0_MIC2_EN_MASK                          (0x1UL<<16)
#define DEV_ADC_MIC_CTRL0_MIC1_GAIN_MASK                        (0x7UL<<12)
#define DEV_ADC_MIC_CTRL0_MIC1_MODE_MIC_MIX                     (0x0UL<<10)
#define DEV_ADC_MIC_CTRL0_MIC1_MODE_SINGLE_N                    (0x1UL<<10)
#define DEV_ADC_MIC_CTRL0_MIC1_MODE_SINGLE_P                    (0x2UL<<10)
#define DEV_ADC_MIC_CTRL0_MIC1_MODE_DIFFERENT                   (0x3UL<<10)
#define DEV_ADC_MIC_CTRL0_MIC1_MODE_MASK                        (0x3UL<<10)
#define DEV_ADC_MIC_CTRL0_MIC1_EN_DISABLE                       (0x0UL<<8)
#define DEV_ADC_MIC_CTRL0_MIC1_EN_ENABLE                        (0x1UL<<8)
#define DEV_ADC_MIC_CTRL0_MIC1_EN_MASK                          (0x1UL<<8)
#define DEV_ADC_MIC_CTRL0_MIC0_GAIN_MASK                        (0x7UL<<4)
#define DEV_ADC_MIC_CTRL0_MIC0_MODE_MIC_MIX                     (0x0UL<<2)
#define DEV_ADC_MIC_CTRL0_MIC0_MODE_SINGLE_N                    (0x1UL<<2)
#define DEV_ADC_MIC_CTRL0_MIC0_MODE_SINGLE_P                    (0x2UL<<2)
#define DEV_ADC_MIC_CTRL0_MIC0_MODE_DIFFERENT                   (0x3UL<<2)
#define DEV_ADC_MIC_CTRL0_MIC0_MODE_MASK                        (0x3UL<<2)
#define DEV_ADC_MIC_CTRL0_MIC0_EN_DISABLE                       (0x0UL<<0)
#define DEV_ADC_MIC_CTRL0_MIC0_EN_ENABLE                        (0x1UL<<0)
#define DEV_ADC_MIC_CTRL0_MIC0_EN_MASK                          (0x1UL<<0)
/****ADC_MIC_CTRL0 end****/


/***********************************ADC_MIC_CTRL1***********************************/
#define DEV_ADC_MIC_CTRL1_MIC_CAP_CHG_DISABLE                   (0x0UL<<8)
#define DEV_ADC_MIC_CTRL1_MIC_CAP_CHG_ENABLE                    (0x1UL<<8)
#define DEV_ADC_MIC_CTRL1_MIC_CAP_CHG_MASK                      (0x1UL<<8)
#define DEV_ADC_MIC_CTRL1_MIC_MIX_BYP_EN_MIX                    (0x0UL<<7)
#define DEV_ADC_MIC_CTRL1_MIC_MIX_BYP_EN_MIXBYPASS              (0x1UL<<7)
#define DEV_ADC_MIC_CTRL1_MIC_MIX_BYP_EN_MASK                   (0x1UL<<7)
#define DEV_ADC_MIC_CTRL1_MIC_BYP_EN_MIC                        (0x0UL<<6)
#define DEV_ADC_MIC_CTRL1_MIC_BYP_EN_MICBYPASS                  (0x1UL<<6)
#define DEV_ADC_MIC_CTRL1_MIC_BYP_EN_MASK                       (0x1UL<<6)
#define DEV_ADC_MIC_CTRL1_MIC_IBIAS_CTRL_5UA                    (0x0UL<<4)
#define DEV_ADC_MIC_CTRL1_MIC_IBIAS_CTRL_10UA                   (0x1UL<<4)
#define DEV_ADC_MIC_CTRL1_MIC_IBIAS_CTRL_15UA                   (0x2UL<<4)
#define DEV_ADC_MIC_CTRL1_MIC_IBIAS_CTRL_2_5UA                  (0x3UL<<4)
#define DEV_ADC_MIC_CTRL1_MIC_IBIAS_CTRL_MASK                   (0x3UL<<4)
#define DEV_ADC_MIC_CTRL1_MIC_PD_STUP_ENABLESTARTUP             (0x0UL<<3)
#define DEV_ADC_MIC_CTRL1_MIC_PD_STUP_POWERDOWNSTARTUP          (0x1UL<<3)
#define DEV_ADC_MIC_CTRL1_MIC_PD_STUP_MASK                      (0x1UL<<3)
#define DEV_ADC_MIC_CTRL1_MIC_VCMI_SEL_SELECTVCM                (0x0UL<<2)
#define DEV_ADC_MIC_CTRL1_MIC_VCMI_SEL_SELECTVREF_VMIC          (0x1UL<<2)
#define DEV_ADC_MIC_CTRL1_MIC_VCMI_SEL_MASK                     (0x1UL<<2)
#define DEV_ADC_MIC_CTRL1_MIC_VCMI_CHOP_EN_ENABLE               (0x1UL<<1)
#define DEV_ADC_MIC_CTRL1_MIC_VCMI_CHOP_EN_DISABLE              (0x0UL<<1)
#define DEV_ADC_MIC_CTRL1_MIC_VCMI_CHOP_EN_MASK                 (0x1UL<<1)
#define DEV_ADC_MIC_CTRL1_MIC_CHOP_EN_ENABLE                    (0x1UL<<0)
#define DEV_ADC_MIC_CTRL1_MIC_CHOP_EN_DISABLE                   (0x0UL<<0)
#define DEV_ADC_MIC_CTRL1_MIC_CHOP_EN_MASK                      (0x1UL<<0)
/****ADC_MIC_CTRL1 end****/


/***********************************ADC_MIX_CTRL0***********************************/
#define DEV_ADC_MIX_CTRL0_MIX1_GAIN_4_5DB                       (0x0UL<<12)
#define DEV_ADC_MIX_CTRL0_MIX1_GAIN_3DB                         (0x1UL<<12)
#define DEV_ADC_MIX_CTRL0_MIX1_GAIN_1_5DB                       (0x2UL<<12)
#define DEV_ADC_MIX_CTRL0_MIX1_GAIN_0DB                         (0x3UL<<12)
#define DEV_ADC_MIX_CTRL0_MIX1_GAIN_MASK                        (0xfUL<<12)
#define DEV_ADC_MIX_CTRL0_MIX1_MIC2_EN_ENABLE                   (0x1UL<<11)
#define DEV_ADC_MIX_CTRL0_MIX1_MIC2_EN_DISABLE                  (0x0UL<<11)
#define DEV_ADC_MIX_CTRL0_MIX1_MIC2_EN_MASK                     (0x1UL<<11)
#define DEV_ADC_MIX_CTRL0_MIX1_MIC1_EN_ENABLE                   (0x1UL<<10)
#define DEV_ADC_MIX_CTRL0_MIX1_MIC1_EN_DISABLE                  (0x0UL<<10)
#define DEV_ADC_MIX_CTRL0_MIX1_MIC1_EN_MASK                     (0x1UL<<10)
#define DEV_ADC_MIX_CTRL0_MIX1_MIC0_EN_ENABLE                   (0x1UL<<9)
#define DEV_ADC_MIX_CTRL0_MIX1_MIC0_EN_DISABLE                  (0x0UL<<9)
#define DEV_ADC_MIX_CTRL0_MIX1_MIC0_EN_MASK                     (0x1UL<<9)
#define DEV_ADC_MIX_CTRL0_MIX1_EN_ENABLE                        (0x1UL<<8)
#define DEV_ADC_MIX_CTRL0_MIX1_EN_DISABLE                       (0x0UL<<8)
#define DEV_ADC_MIX_CTRL0_MIX1_EN_MASK                          (0x1UL<<8)
#define DEV_ADC_MIX_CTRL0_MIX0_GAIN_4_5DB                       (0x0UL<<4)
#define DEV_ADC_MIX_CTRL0_MIX0_GAIN_3DB                         (0x1UL<<4)
#define DEV_ADC_MIX_CTRL0_MIX0_GAIN_1_5DB                       (0x2UL<<4)
#define DEV_ADC_MIX_CTRL0_MIX0_GAIN_0DB                         (0x3UL<<4)
#define DEV_ADC_MIX_CTRL0_MIX0_GAIN_MASK                        (0xfUL<<4)
#define DEV_ADC_MIX_CTRL0_MIX0_MIC2_EN_ENABLE                   (0x1UL<<3)
#define DEV_ADC_MIX_CTRL0_MIX0_MIC2_EN_DISABLE                  (0x0UL<<3)
#define DEV_ADC_MIX_CTRL0_MIX0_MIC2_EN_MASK                     (0x1UL<<3)
#define DEV_ADC_MIX_CTRL0_MIX0_MIC1_EN_ENABLE                   (0x1UL<<2)
#define DEV_ADC_MIX_CTRL0_MIX0_MIC1_EN_DISABLE                  (0x0UL<<2)
#define DEV_ADC_MIX_CTRL0_MIX0_MIC1_EN_MASK                     (0x1UL<<2)
#define DEV_ADC_MIX_CTRL0_MIX0_MIC0_EN_ENABLE                   (0x1UL<<1)
#define DEV_ADC_MIX_CTRL0_MIX0_MIC0_EN_DISABLE                  (0x0UL<<1)
#define DEV_ADC_MIX_CTRL0_MIX0_MIC0_EN_MASK                     (0x1UL<<1)
#define DEV_ADC_MIX_CTRL0_MIX0_EN_ENABLE                        (0x1UL<<0)
#define DEV_ADC_MIX_CTRL0_MIX0_EN_DISABLE                       (0x0UL<<0)
#define DEV_ADC_MIX_CTRL0_MIX0_EN_MASK                          (0x1UL<<0)
/****ADC_MIX_CTRL0 end****/


/***********************************ADC_MIX_CTRL1***********************************/
#define DEV_ADC_MIX_CTRL1_MIX_IBIAS_CTRL_5UA                    (0x0UL<<4)
#define DEV_ADC_MIX_CTRL1_MIX_IBIAS_CTRL_2_5UA                  (0x1UL<<4)
#define DEV_ADC_MIX_CTRL1_MIX_IBIAS_CTRL_10UA                   (0x2UL<<4)
#define DEV_ADC_MIX_CTRL1_MIX_IBIAS_CTRL_15UA                   (0x3UL<<4)
#define DEV_ADC_MIX_CTRL1_MIX_IBIAS_CTRL_MASK                   (0x3UL<<4)
#define DEV_ADC_MIX_CTRL1_ZC_COMP_EN_DISABLE                    (0x0UL<<2)
#define DEV_ADC_MIX_CTRL1_ZC_COMP_EN_ENABLE                     (0x1UL<<2)
#define DEV_ADC_MIX_CTRL1_ZC_COMP_EN_MASK                       (0x1UL<<2)
#define DEV_ADC_MIX_CTRL1_MIX_PD_STUP_ENABLESTARTUP             (0x0UL<<1)
#define DEV_ADC_MIX_CTRL1_MIX_PD_STUP_POWERDOWNSTARTUP          (0x1UL<<1)
#define DEV_ADC_MIX_CTRL1_MIX_PD_STUP_MASK                      (0x1UL<<1)
#define DEV_ADC_MIX_CTRL1_MIX_CHOP_EN_DISABLE                   (0x0UL<<0)
#define DEV_ADC_MIX_CTRL1_MIX_CHOP_EN_ENABLE                    (0x1UL<<0)
#define DEV_ADC_MIX_CTRL1_MIX_CHOP_EN_MASK                      (0x1UL<<0)
/****ADC_MIX_CTRL1 end****/


/***********************************ADC_SDM_CTRL0***********************************/
#define DEV_ADC_SDM_CTRL0_ADC_START                             (0x1UL<<0)
/****ADC_SDM_CTRL0 end****/


/***********************************ADC_SDM_CTRL1***********************************/
#define DEV_ADC_SDM_CTRL1_ADC1_CLKDIV_SEL_CLK_1                 (0x0UL<<26)
#define DEV_ADC_SDM_CTRL1_ADC1_CLKDIV_SEL_CLK_2                 (0x1UL<<26)
#define DEV_ADC_SDM_CTRL1_ADC1_CLKDIV_SEL_CLK_3                 (0x2UL<<26)
#define DEV_ADC_SDM_CTRL1_ADC1_CLKDIV_SEL_CLK_6                 (0x3UL<<26)
#define DEV_ADC_SDM_CTRL1_ADC1_CLKDIV_SEL_MASK                  (0x3UL<<26)
#define DEV_ADC_SDM_CTRL1_ADC0_CLKDIV_SEL_CLK_1                 (0x0UL<<24)
#define DEV_ADC_SDM_CTRL1_ADC0_CLKDIV_SEL_CLK_2                 (0x1UL<<24)
#define DEV_ADC_SDM_CTRL1_ADC0_CLKDIV_SEL_CLK_3                 (0x2UL<<24)
#define DEV_ADC_SDM_CTRL1_ADC0_CLKDIV_SEL_CLK_6                 (0x3UL<<24)
#define DEV_ADC_SDM_CTRL1_ADC0_CLKDIV_SEL_MASK                  (0x3UL<<24)
#define DEV_ADC_SDM_CTRL1_ADC_VREF_CHG                          (0x1UL<<22)
#define DEV_ADC_SDM_CTRL1_ADC_AMPDET_DITHER                     (0x1UL<<21)
#define DEV_ADC_SDM_CTRL1_ADC_AMPDET_DEM                        (0x1UL<<20)
#define DEV_ADC_SDM_CTRL1_ADC_DITHER_SEL_MASK                   (0x3UL<<18)
#define DEV_ADC_SDM_CTRL1_ADC_DITHER_EN_DISABLE                 (0x0UL<<16)
#define DEV_ADC_SDM_CTRL1_ADC_DITHER_EN_ENABLE                  (0x1UL<<16)
#define DEV_ADC_SDM_CTRL1_ADC_DITHER_EN_MASK                    (0x1UL<<16)
#define DEV_ADC_SDM_CTRL1_ADC_BKDEM_EN_DISABLE                  (0x0UL<<15)
#define DEV_ADC_SDM_CTRL1_ADC_BKDEM_EN_ENABLE                   (0x1UL<<15)
#define DEV_ADC_SDM_CTRL1_ADC_BKDEM_EN_MASK                     (0x1UL<<15)
#define DEV_ADC_SDM_CTRL1_ADC_DEM_PD_DISABLE                    (0x1UL<<14)
#define DEV_ADC_SDM_CTRL1_ADC_DEM_PD_ENABLE                     (0x0UL<<14)
#define DEV_ADC_SDM_CTRL1_ADC_DEM_PD_MASK                       (0x1UL<<14)
#define DEV_ADC_SDM_CTRL1_ADC_NONOV_1N                          (0x0UL<<12)
#define DEV_ADC_SDM_CTRL1_ADC_NONOV_2N                          (0x1UL<<12)
#define DEV_ADC_SDM_CTRL1_ADC_NONOV_3N                          (0x2UL<<12)
#define DEV_ADC_SDM_CTRL1_ADC_NONOV_5N                          (0x3UL<<12)
#define DEV_ADC_SDM_CTRL1_ADC_NONOV_MASK                        (0x3UL<<12)
#define DEV_ADC_SDM_CTRL1_ADC_CHOP_DIV_8                        (0x0UL<<10)
#define DEV_ADC_SDM_CTRL1_ADC_CHOP_DIV_16                       (0x1UL<<10)
#define DEV_ADC_SDM_CTRL1_ADC_CHOP_DIV_32                       (0x2UL<<10)
#define DEV_ADC_SDM_CTRL1_ADC_CHOP_DIV_64                       (0x3UL<<10)
#define DEV_ADC_SDM_CTRL1_ADC_CHOP_DIV_MASK                     (0x3UL<<10)
#define DEV_ADC_SDM_CTRL1_ADC_CHOP_EN_DISABLE                   (0x0UL<<8)
#define DEV_ADC_SDM_CTRL1_ADC_CHOP_EN_ENABLE                    (0x1UL<<8)
#define DEV_ADC_SDM_CTRL1_ADC_CHOP_EN_MASK                      (0x1UL<<8)
#define DEV_ADC_SDM_CTRL1_ADC_IBOTA2_CTRL_5UA                   (0x0UL<<6)
#define DEV_ADC_SDM_CTRL1_ADC_IBOTA2_CTRL_10UA                  (0x1UL<<6)
#define DEV_ADC_SDM_CTRL1_ADC_IBOTA2_CTRL_15UA                  (0x2UL<<6)
#define DEV_ADC_SDM_CTRL1_ADC_IBOTA2_CTRL_2_5UA                 (0x3UL<<6)
#define DEV_ADC_SDM_CTRL1_ADC_IBOTA2_CTRL_MASK                  (0x3UL<<6)
#define DEV_ADC_SDM_CTRL1_ADC_IBOTA1_CTRL_5UA                   (0x0UL<<4)
#define DEV_ADC_SDM_CTRL1_ADC_IBOTA1_CTRL_10UA                  (0x1UL<<4)
#define DEV_ADC_SDM_CTRL1_ADC_IBOTA1_CTRL_15UA                  (0x2UL<<4)
#define DEV_ADC_SDM_CTRL1_ADC_IBOTA1_CTRL_2_5UA                 (0x3UL<<4)
#define DEV_ADC_SDM_CTRL1_ADC_IBOTA1_CTRL_MASK                  (0x3UL<<4)
#define DEV_ADC_SDM_CTRL1_ADC1_EN_ENABLE                        (0x1UL<<1)
#define DEV_ADC_SDM_CTRL1_ADC1_EN_DISABLE                       (0x0UL<<1)
#define DEV_ADC_SDM_CTRL1_ADC1_EN_MASK                          (0x1UL<<1)
#define DEV_ADC_SDM_CTRL1_ADC0_EN_ENABLE                        (0x1UL<<0)
#define DEV_ADC_SDM_CTRL1_ADC0_EN_DISABLE                       (0x0UL<<0)
#define DEV_ADC_SDM_CTRL1_ADC0_EN_MASK                          (0x1UL<<0)
/****ADC_SDM_CTRL1 end****/


/***********************************ADC_RSVD_CTRL***********************************/
#define DEV_ADC_RSVD_CTRL_ADC1_RSVD_MASK                        (0x3fUL<<8)
#define DEV_ADC_RSVD_CTRL_ADC0_RSVD_MASK                        (0x3fUL<<0)
/****ADC_RSVD_CTRL end****/


/***********************************ADC_VMIC0_CTRL***********************************/
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_2_77V                      (0x0UL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_2_71V                      (0x1UL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_2_59V                      (0x2UL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_2_49V                      (0x3UL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_2_40V                      (0x4UL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_2_29V                      (0x5UL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_2_21V                      (0x6UL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_2_10V                      (0x7UL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_2_00V                      (0x8UL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_1_91V                      (0x9UL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_1_81V                      (0xaUL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_1_71V                      (0xbUL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_1_60V                      (0xcUL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_1_50V                      (0xdUL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_VOL_MASK                       (0xfUL<<4)
#define DEV_ADC_VMIC0_CTRL_VMIC0_REF_SEL_USEVREF_VMIC           (0x0UL<<3)
#define DEV_ADC_VMIC0_CTRL_VMIC0_REF_SEL_USEVCM                 (0x1UL<<3)
#define DEV_ADC_VMIC0_CTRL_VMIC0_REF_SEL_MASK                   (0x1UL<<3)
#define DEV_ADC_VMIC0_CTRL_VMIC0_DISCHG_VMIC0DISCHARGEENABLE    (0x1UL<<2)
#define DEV_ADC_VMIC0_CTRL_VMIC0_DISCHG_VMIC0DISCHARGEDISABLE   (0x0UL<<2)
#define DEV_ADC_VMIC0_CTRL_VMIC0_DISCHG_MASK                    (0x1UL<<2)
#define DEV_ADC_VMIC0_CTRL_VMIC0_BYPASS_ENABLEBYPASS            (0x1UL<<1)
#define DEV_ADC_VMIC0_CTRL_VMIC0_BYPASS_DISABLEBYPASS           (0x0UL<<1)
#define DEV_ADC_VMIC0_CTRL_VMIC0_BYPASS_MASK                    (0x1UL<<1)
#define DEV_ADC_VMIC0_CTRL_VMIC0_EN_ENABLE                      (0x1UL<<0)
#define DEV_ADC_VMIC0_CTRL_VMIC0_EN_DISABLE                     (0x0UL<<0)
#define DEV_ADC_VMIC0_CTRL_VMIC0_EN_MASK                        (0x1UL<<0)
/****ADC_VMIC0_CTRL end****/


/***********************************ADC_VMIC1_CTRL***********************************/
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_2_77V                      (0x0UL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_2_71V                      (0x1UL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_2_59V                      (0x2UL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_2_49V                      (0x3UL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_2_40V                      (0x4UL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_2_29V                      (0x5UL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_2_21V                      (0x6UL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_2_10V                      (0x7UL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_2_00V                      (0x8UL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_1_91V                      (0x9UL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_1_81V                      (0xaUL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_1_71V                      (0xbUL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_1_60V                      (0xcUL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_1_50V                      (0xdUL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_VOL_MASK                       (0xfUL<<4)
#define DEV_ADC_VMIC1_CTRL_VMIC1_REF_SEL_USEVREF_VMIC           (0x0UL<<3)
#define DEV_ADC_VMIC1_CTRL_VMIC1_REF_SEL_USEVCM                 (0x1UL<<3)
#define DEV_ADC_VMIC1_CTRL_VMIC1_REF_SEL_MASK                   (0x1UL<<3)
#define DEV_ADC_VMIC1_CTRL_VMIC1_DISCHG_VMIC1DISCHARGEENABLE    (0x1UL<<2)
#define DEV_ADC_VMIC1_CTRL_VMIC1_DISCHG_VMIC1DISCHARGEDISABLE   (0x0UL<<2)
#define DEV_ADC_VMIC1_CTRL_VMIC1_DISCHG_MASK                    (0x1UL<<2)
#define DEV_ADC_VMIC1_CTRL_VMIC1_BYPASS_ENABLEBYPASS            (0x1UL<<1)
#define DEV_ADC_VMIC1_CTRL_VMIC1_BYPASS_DISABLEBYPASS           (0x0UL<<1)
#define DEV_ADC_VMIC1_CTRL_VMIC1_BYPASS_MASK                    (0x1UL<<1)
#define DEV_ADC_VMIC1_CTRL_VMIC1_EN_ENABLE                      (0x1UL<<0)
#define DEV_ADC_VMIC1_CTRL_VMIC1_EN_DISABLE                     (0x0UL<<0)
#define DEV_ADC_VMIC1_CTRL_VMIC1_EN_MASK                        (0x1UL<<0)
/****ADC_VMIC1_CTRL end****/


/***********************************ADC_VMIC_RAMP0***********************************/
#define DEV_ADC_VMIC_RAMP0_RAMP_TIME_MASK                       (0xffffUL<<16)
#define DEV_ADC_VMIC_RAMP0_FAST_STUP_VMIC_DISABLE               (0x0UL<<4)
#define DEV_ADC_VMIC_RAMP0_FAST_STUP_VMIC_ENABLE                (0x1UL<<4)
#define DEV_ADC_VMIC_RAMP0_FAST_STUP_VMIC_MASK                  (0x1UL<<4)
#define DEV_ADC_VMIC_RAMP0_VMIC1_RAMP_DN_EN_DISABLE             (0x0UL<<3)
#define DEV_ADC_VMIC_RAMP0_VMIC1_RAMP_DN_EN_ENABLE              (0x1UL<<3)
#define DEV_ADC_VMIC_RAMP0_VMIC1_RAMP_DN_EN_MASK                (0x1UL<<3)
#define DEV_ADC_VMIC_RAMP0_VMIC1_RAMP_UP_EN_DISABLE             (0x0UL<<2)
#define DEV_ADC_VMIC_RAMP0_VMIC1_RAMP_UP_EN_ENABLE              (0x1UL<<2)
#define DEV_ADC_VMIC_RAMP0_VMIC1_RAMP_UP_EN_MASK                (0x1UL<<2)
#define DEV_ADC_VMIC_RAMP0_VMIC0_RAMP_DN_EN_DISABLE             (0x0UL<<1)
#define DEV_ADC_VMIC_RAMP0_VMIC0_RAMP_DN_EN_ENABLE              (0x1UL<<1)
#define DEV_ADC_VMIC_RAMP0_VMIC0_RAMP_DN_EN_MASK                (0x1UL<<1)
#define DEV_ADC_VMIC_RAMP0_VMIC0_RAMP_UP_EN_DISABLE             (0x0UL<<0)
#define DEV_ADC_VMIC_RAMP0_VMIC0_RAMP_UP_EN_ENABLE              (0x1UL<<0)
#define DEV_ADC_VMIC_RAMP0_VMIC0_RAMP_UP_EN_MASK                (0x1UL<<0)
/****ADC_VMIC_RAMP0 end****/


/***********************************ADC_VMIC_RAMP1***********************************/
#define DEV_ADC_VMIC_RAMP1_TOTAL_NUM_MASK                       (0xffffUL<<16)
#define DEV_ADC_VMIC_RAMP1_HIGH_NUM_MASK                        (0xffffUL<<0)
/****ADC_VMIC_RAMP1 end****/


/***********************************ADC_ANA_PD***********************************/
#define DEV_ADC_ANA_PD_OUT_ZEROCROSS                            (0x1UL<<4)
#define DEV_ADC_ANA_PD_ADC1_OVF                                 (0x1UL<<1)
#define DEV_ADC_ANA_PD_ADC0_OVF                                 (0x1UL<<0)
/****ADC_ANA_PD end****/


/***********************************DEV_ADC register***********************************/
typedef struct
{
    __IO    uint32_t    CHNn_CFG[4];                             /* 0x0    ADC Channel 0 Configure */
    __IO    uint32_t    CFG;                                     /* 0x10    ADC Configure */
    __IO    uint32_t    CTL;                                     /* 0x14    ADC Control */
    __IO    uint32_t    IE;                                      /* 0x18    ADC Interrupt Enable */
    __IO    uint32_t    PD;                                      /* 0x1c    ADC Interrupt Pending */
    __I     uint32_t    STA;                                     /* 0x20    ADC Status */
    __I     uint32_t    RBUF;                                    /* 0x24    ADCRBUF */
    uint32_t    RESERVED0[2];
    __IO    uint32_t    GAIN_CFG;                                /* 0x30    ADC Gain Configure */
    __IO    uint32_t    PEAK_AT;                                 /* 0x34    ADC Peak Attack. Time */
    __IO    uint32_t    PEAK_RT;                                 /* 0x38    ADC Peak Release Time */
    __IO    uint32_t    GAIN_AT;                                 /* 0x3c    ADC Gain Attack. Time */
    __IO    uint32_t    GAIN_RT;                                 /* 0x40    ADC Gain Release Time */
    uint32_t    RESERVED1[3];
    __IO    uint32_t    BIST_EN;                                 /* 0x50    ADC BIST Enable */
    __IO    uint32_t    BIST_RM;                                 /* 0x54    ADC BIST Read Margin */
    __I     uint32_t    BIST_DONE;                               /* 0x58    ADC BIST done */
    __I     uint32_t    BIST_FAIL;                               /* 0x5c    ADC BIST fail */
    uint32_t    RESERVED2[8];
    __IO    uint32_t    MIC_CTRL0;                               /* 0x80    ADC Mic Control 0 */
    __IO    uint32_t    MIC_CTRL1;                               /* 0x84    ADC Mic Control 1 */
    __IO    uint32_t    MIX_CTRL0;                               /* 0x88    ADC Mix Control 0 */
    __IO    uint32_t    MIX_CTRL1;                               /* 0x8c    ADC Mix Control 1 */
    __IO    uint32_t    SDM_CTRL0;                               /* 0x90    ADC SDM Control 0 */
    __IO    uint32_t    SDM_CTRL1;                               /* 0x94    ADC SDM Control 1 */
    __IO    uint32_t    RSVD_CTRL;                               /* 0x98    ADC RSVD Control */
    __IO    uint32_t    VMIC0_CTRL;                              /* 0x9c    ADC VMIC0 Control */
    __IO    uint32_t    VMIC1_CTRL;                              /* 0xa0    ADC VMIC1 Control */
    __IO    uint32_t    VMIC_RAMP0;                              /* 0xa4    ADC VMIC Ramp Control 0 */
    __IO    uint32_t    VMIC_RAMP1;                              /* 0xa8    ADC VMIC Ramp Control 1 */
    uint32_t    RESERVED3[17];
    __IO    uint32_t    ANA_PD;                                  /* 0xf0    ADC Analog Status */
} DEV_ADC_RegDef;
/****DEV_ADC end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
