#include "platform.h"
#include "hal_headfile.h"
#include "board.h"
#include "system.h"
#include "heap_5.h"
#include "debug.h"
#include "timer.h"
#include "Plxc_Algo_Api.h"
#include "config.h"


extern void system_wakeup_process(void);

volatile uint8_t BaseTime_2ms_Cnt = 0;
volatile uint8_t BaseTime_10ms_Cnt = 0;
volatile uint8_t BaseTime_100ms_Cnt = 0;

uint32_t heap[HEAP_5_SIZE / 4] = { 0 };
HeapRegion_t xHeapRegions[] =
{ { (uint8_t *) heap, sizeof(heap) }, { NULL, 0 } };


void disable_debug_pin(void)
{
    DEV_GPIO->CTL[4] = 10;
    DEV_GPIO->CTL[5] = 10;
    DEV_GPIO->CTL[6] = 10;
    DEV_GPIO->CTL[7] = 10;
}

void riscv_clock_init(void)
{
    /* set sys clk from Osc_dev*/
    cmu_sys_set_clk(CMU_Clock_OSC_DEV, CMU_Clk_Div_1, CMU_Clk_Div_1);
    /* osc xtal config */
    cmu_set_oscxtal();
    cmu_clk_ready_detect(CMU_Clock_OSC_XTAL);

    while (cmu_get_clk_detect(CMU_Clock_OSC_XTAL) != RESET) {;}

#ifdef ENTER_DVDD_MODE
    /* set vdd voltage */
    pmu_dvdd_voltage_config(PMU_DVDD_VOL_1_4V);
#else
    //外部DCDC给DVDD
    delay_us(24 * MHz, 100);
    AON_PMU->PWR_CTL |= (1 << 25);
    delay_us(24 * MHz, 20);
    AON_PMU->PWR_CTL &= ~(1 << 10);
    AON_PMU->VOL_CTL_f.DVDD_VOL = 6;
#endif
    /* set pllï¼Œand wait pll_core stable */
    cmu_set_pllcore(CMU_Clock_OSC_XTAL, CPU_MAX_FREQ);
    cmu_clk_ready_detect(CMU_Clock_PLL_CORE);

    while (cmu_get_clk_detect(CMU_Clock_PLL_CORE) != RESET) {;}

    /* set sys clk and cpu clk, cpu_clk = pll_core/1, sys_clk = cpu_clk/2 */
    cmu_sys_set_clk(CMU_Clock_PLL_CORE, CMU_Clk_Div_1, CMU_Clk_Div_2);
    /* set norc clk, norc_clk = sys_clk/2 */
    //cmu_nor_set_clk(CMU_Clock_SYS, CMU_Clk_Div_2);
    cmu_enable_usb_clock();
    DEV_NORC->CTL_f.DELAY_CHAIN = 0x0a;
    DEV_CMU->NOR0CLK = DEV_CMU_NOR0CLK_DIV_4 | DEV_CMU_NOR0CLK_SEL_PLL_USB;
}


void board_init(void)
{
    disable_debug_pin();
    DEV_CMU->CLKEN0 &= ~DEV_CMU_CLKEN0_DMA;
    DEV_RMU->RSTEN0 &= ~DEV_RMU_RSTEN0_DMA;
    DEV_CMU->CLKEN0 |= DEV_CMU_CLKEN0_DMA;
    DEV_RMU->RSTEN0 |= DEV_RMU_RSTEN0_DMA;
    riscv_clock_init();
    GIE_ENABLE();
    vPortDefineHeapRegions(xHeapRegions);
    get_param_from_ext();
    debug_uart_init();
    DEV_RMU->RSTEN0 &= ~DEV_RMU_RSTEN0_SRC;
    DEV_RMU->RSTEN0 |=  DEV_RMU_RSTEN0_SRC;
    DEV_CMU->CLKEN0 |=  DEV_CMU_CLKEN0_SRC;
    system_wakeup_process();
}

int main(void)
{
    board_init();
	hal_watchdog_init();
    user_init();
    timer_init();
    debug("timer_init\r\n");
    while (1)
    {
        //plxc_algo_fsm();

        if (BaseTime_2ms_Cnt <= _2MS_BASE_CNT)
            continue;

        //2ms 执行一次
        user_2ms_handler();
        BaseTime_2ms_Cnt -= _2MS_BASE_CNT;
        BaseTime_10ms_Cnt++;

        if (BaseTime_10ms_Cnt <= _10MS_BASE_CNT)
            continue;

        //10ms 执行一次
        user_10ms_handler();
        BaseTime_10ms_Cnt -= _10MS_BASE_CNT;
        BaseTime_100ms_Cnt++;

        if (BaseTime_100ms_Cnt <= _100MS_BASE_CNT)
            continue;

        BaseTime_100ms_Cnt -= _100MS_BASE_CNT;
        //100ms 执行一次
        user_100ms_handler();
		hal_watchdog_keep_alive();
    }
}


