#ifndef __DEV_DMAC_H__
#define __DEV_DMAC_H__

#include "sp2cw3.h"
/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************DMA_CHNn_SSA***********************************/
#define DEV_DMAC_DMA_CHNn_SSA_SRC_START_ADDR_MASK               (0xffffffffUL<<0)
/****DMA_CHNn_SSA end****/


/***********************************DMA_CHNn_SOA***********************************/
#define DEV_DMAC_DMA_CHNn_SOA_SRC_SLOT_OFFSET(_total_)          (((_total_)-1)<<16)
#define DEV_DMAC_DMA_CHNn_SOA_SRC_SLOT_OFFSET_MASK              (0xffffUL<<16)
#define DEV_DMAC_DMA_CHNn_SOA_SRC_WORD_OFFSET(_total_)          (((_total_)-1)<<0)
#define DEV_DMAC_DMA_CHNn_SOA_SRC_WORD_OFFSET_MASK              (0xffffUL<<0)
/****DMA_CHNn_SOA end****/


/***********************************DMA_CHNn_DSA***********************************/
#define DEV_DMAC_DMA_CHNn_DSA_DST_START_ADDR_MASK               (0xffffffffUL<<0)
/****DMA_CHNn_DSA end****/


/***********************************DMA_CHNn_DOA***********************************/
#define DEV_DMAC_DMA_CHNn_DOA_DST_SLOT_OFFSET(_total_)          (((_total_)-1)<<16)
#define DEV_DMAC_DMA_CHNn_DOA_DST_SLOT_OFFSET_MASK              (0xffffUL<<16)
#define DEV_DMAC_DMA_CHNn_DOA_DST_WORD_OFFSET(_total_)          (((_total_)-1)<<0)
#define DEV_DMAC_DMA_CHNn_DOA_DST_WORD_OFFSET_MASK              (0xffffUL<<0)
/****DMA_CHNn_DOA end****/


/***********************************DMA_CHNn_LEN***********************************/
#define DEV_DMAC_DMA_CHNn_LEN_SLOT_NUM(_total_)                 (((_total_)-1)<<16)
#define DEV_DMAC_DMA_CHNn_LEN_SLOT_NUM_MASK                     (0xffffUL<<16)
#define DEV_DMAC_DMA_CHNn_LEN_BYTE_NUM(_total_)                 (((_total_)-1)<<0)
#define DEV_DMAC_DMA_CHNn_LEN_BYTE_NUM_MASK                     (0xffffUL<<0)
/****DMA_CHNn_LEN end****/


/***********************************DMA_CHNn_CFG***********************************/
#define DEV_DMAC_DMA_CHNn_CFG_Reducer_NORMAL_BURSTTRANSFER      (0x0UL<<30)
#define DEV_DMAC_DMA_CHNn_CFG_Reducer_PIPELINESINGLETRANSFER    (0x1UL<<30)
#define DEV_DMAC_DMA_CHNn_CFG_Reducer_MASK                      (0x1UL<<30)
#define DEV_DMAC_DMA_CHNn_CFG_CLK_ON_CLOCKISGATEDIFDMADISABLED  (0x0UL<<29)
#define DEV_DMAC_DMA_CHNn_CFG_CLK_ON_CLOCKALWAYSON              (0x1UL<<29)
#define DEV_DMAC_DMA_CHNn_CFG_CLK_ON_MASK                       (0x1UL<<29)
#define DEV_DMAC_DMA_CHNn_CFG_PAUSE_WORK                        (0x0UL<<28)
#define DEV_DMAC_DMA_CHNn_CFG_PAUSE_PAUSE                       (0x1UL<<28)
#define DEV_DMAC_DMA_CHNn_CFG_PAUSE_MASK                        (0x1UL<<28)
#define DEV_DMAC_DMA_CHNn_CFG_DST_WIDTH_08BIT                   (0x0UL<<26)
#define DEV_DMAC_DMA_CHNn_CFG_DST_WIDTH_16BIT                   (0x1UL<<26)
#define DEV_DMAC_DMA_CHNn_CFG_DST_WIDTH_24BIT                   (0x2UL<<26)
#define DEV_DMAC_DMA_CHNn_CFG_DST_WIDTH_32BIT                   (0x3UL<<26)
#define DEV_DMAC_DMA_CHNn_CFG_DST_WIDTH_MASK                    (0x3UL<<26)
#define DEV_DMAC_DMA_CHNn_CFG_DST_DLS_LOW_24BIT                 (0x0UL<<25)
#define DEV_DMAC_DMA_CHNn_CFG_DST_DLS_HIGH24BIT                 (0x1UL<<25)
#define DEV_DMAC_DMA_CHNn_CFG_DST_DLS_MASK                      (0x1UL<<25)
#define DEV_DMAC_DMA_CHNn_CFG_DST_IFS_MASK                      (0x1fUL<<20)
#define DEV_DMAC_DMA_CHNn_CFG_DST_BURST_LEN_SINGLE              (0x0UL<<18)
#define DEV_DMAC_DMA_CHNn_CFG_DST_BURST_LEN_BURST2              (0x1UL<<18)
#define DEV_DMAC_DMA_CHNn_CFG_DST_BURST_LEN_BURST4              (0x2UL<<18)
#define DEV_DMAC_DMA_CHNn_CFG_DST_BURST_LEN_BURST8              (0x3UL<<18)
#define DEV_DMAC_DMA_CHNn_CFG_DST_BURST_LEN_MASK                (0x3UL<<18)
#define DEV_DMAC_DMA_CHNn_CFG_DST_INC_FIX                       (0x0UL<<17)
#define DEV_DMAC_DMA_CHNn_CFG_DST_INC_INCREMENT                 (0x1UL<<17)
#define DEV_DMAC_DMA_CHNn_CFG_DST_INC_MASK                      (0x1UL<<17)
#define DEV_DMAC_DMA_CHNn_CFG_DST_SLV_MEMORY                    (0x0UL<<16)
#define DEV_DMAC_DMA_CHNn_CFG_DST_SLV_DEVICE                    (0x1UL<<16)
#define DEV_DMAC_DMA_CHNn_CFG_DST_SLV_MASK                      (0x1UL<<16)
#define DEV_DMAC_DMA_CHNn_CFG_RELOAD_DISABLE                    (0x0UL<<15)
#define DEV_DMAC_DMA_CHNn_CFG_RELOAD_ENABLE                     (0x1UL<<15)
#define DEV_DMAC_DMA_CHNn_CFG_RELOAD_MASK                       (0x1UL<<15)
#define DEV_DMAC_DMA_CHNn_CFG_CHN_PRIO_MASK                     (0x7UL<<12)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_WIDTH_08BIT                   (0x0UL<<10)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_WIDTH_16BIT                   (0x1UL<<10)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_WIDTH_24BIT                   (0x2UL<<10)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_WIDTH_32BIT                   (0x3UL<<10)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_WIDTH_MASK                    (0x3UL<<10)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_DLS_LOW_24BIT                 (0x0UL<<9)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_DLS_HIGH24BIT                 (0x1UL<<9)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_DLS_MASK                      (0x1UL<<9)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_IFS_MASK                      (0x1fUL<<4)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_BURST_LEN_SINGLE              (0x0UL<<2)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_BURST_LEN_BURST2              (0x1UL<<2)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_BURST_LEN_BURST4              (0x2UL<<2)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_BURST_LEN_BURST8              (0x3UL<<2)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_BURST_LEN_MASK                (0x3UL<<2)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_INC_FIX                       (0x0UL<<1)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_INC_INCREMENT                 (0x1UL<<1)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_INC_MASK                      (0x1UL<<1)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_SLV_MEMORY                    (0x0UL<<0)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_SLV_DEVICE                    (0x1UL<<0)
#define DEV_DMAC_DMA_CHNn_CFG_SRC_SLV_MASK                      (0x1UL<<0)
/****DMA_CHNn_CFG end****/


/***********************************DMA_CHNn_STA***********************************/
#define DEV_DMAC_DMA_CHNn_STA_RMN_SLOT_CNT_MASK                 (0xffffUL<<16)
#define DEV_DMAC_DMA_CHNn_STA_RMN_BYTE_CNT_MASK                 (0xffffUL<<0)
/****DMA_CHNn_STA end****/


/***********************************DMA_EN***********************************/
#define DEV_DMAC_DMA_EN_CHN_EN_WE_MASK                          (0xffUL<<16)
#define DEV_DMAC_DMA_EN_CHN_EN_MASK                             (0xffUL<<0)
/****DMA_EN end****/


/***********************************DMA_IE***********************************/
#define DEV_DMAC_DMA_IE_SLT_END_IE_MASK                         (0xffUL<<16)
#define DEV_DMAC_DMA_IE_HF_END_IE_MASK                          (0xffUL<<8)
#define DEV_DMAC_DMA_IE_TR_END_IE_MASK                          (0xffUL<<0)
/****DMA_IE end****/


/***********************************DMA_PD***********************************/
#define DEV_DMAC_DMA_PD_SLT_END_PD_MASK                         (0xffUL<<16)
#define DEV_DMAC_DMA_PD_HF_END_PD_MASK                          (0xffUL<<8)
#define DEV_DMAC_DMA_PD_TR_END_PD_MASK                          (0xffUL<<0)
/****DMA_PD end****/


/***********************************DMA_CHN register***********************************/
typedef struct
{
    __IO    uint32_t    SSA;                                     /* 0x0    CHN 0 Source Start Address */
    __IO    uint32_t    SOA;                                     /* 0x4    CHN 0 Source Offset Address */
    __IO    uint32_t    DSA;                                     /* 0x8    CHN 0 Destination Start Address */
    __IO    uint32_t    DOA;                                     /* 0xc    CHN 0 Destination Offset Address */
    __IO    uint32_t    LEN;                                     /* 0x10    CHN 0 Transfer Block Length */
    __IO    uint32_t    CFG;                                     /* 0x14    CHN 0 Configure */
    __I     uint32_t    STA;                                     /* 0x18    CHN 0 Status */
    uint32_t    RESERVED0[57];
} DMA_CHN_RegDef;
/****DMA_CHN end****/

/***********************************DEV_DMAC register***********************************/
typedef struct
{
    DMA_CHN_RegDef    DMA_CHN[8];                              /* 0x0    CHN 0 Source Start Address */
    uint32_t    RESERVED0[512];
    __IO    uint32_t    DMA_EN;                                  /* 0x1000    CHN 2 Source Start Address */
    __IO    uint32_t    DMA_IE;                                  /* 0x1004    CHN 2 Source Offset Address */
    __IO    uint32_t    DMA_PD;                                  /* 0x1008    CHN 2 Destination Start Address */
} DEV_DMAC_RegDef;
/****DEV_DMAC end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/




typedef enum
{
    DMA_Slot_Transfer_End = 1UL << 16,
    DMA_Half_Transfer_End = 1UL << 8,
    DMA_Transfer_End = 1UL,
} dma_it_type_t;

typedef enum
{
    DMA_Device_Sel_None = 0UL,
    DMA_Device_Sel_SPI0_TX = 0UL,
    DMA_Device_Sel_SPI0_RX = 0UL,
    DMA_Device_Sel_SPI1_TX = 1UL,
    DMA_Device_Sel_SPI1_RX = 1UL,
    DMA_Device_Sel_UART0_TX = 2UL,
    DMA_Device_Sel_UART0_RX = 2UL,
    DMA_Device_Sel_UART1_TX = 3UL,
    DMA_Device_Sel_UART1_RX = 3UL,
    DMA_Device_Sel_UART2_TX = 4UL,
    DMA_Device_Sel_UART2_RX = 4UL,
    DMA_Device_Sel_ASI0_TX = 5UL,
    DMA_Device_Sel_ASI0_RX = 5UL,
    DMA_Device_Sel_ASI1_TX = 6UL,
    DMA_Device_Sel_ASI1_RX = 6UL,
    DMA_Device_Sel_PWM_FIFO0 = 7UL,
    DMA_Device_Sel_PWM_FIFO1 = 8UL,
    DMA_Device_Sel_SDC_TX = 9UL,
    DMA_Device_Sel_SDC_RX = 9UL,
    DMA_Device_Sel_DAC_TX = 10UL,
    DMA_Device_Sel_ADC_RX = 10UL,
    DMA_Device_Sel_NOR_RX = 11UL,
    DMA_Device_Sel_SRC_CHN0_TX = 12UL,
    DMA_Device_Sel_SRC_CHN0_RX = 12UL,
    DMA_Device_Sel_SRC_CHN1_TX = 13UL,
    DMA_Device_Sel_SRC_CHN1_RX = 13UL,
    DMA_Device_Sel_USB_TX1 = 16UL,
    DMA_Device_Sel_USB_RX1 = 16UL,
    DMA_Device_Sel_USB_TX2 = 17UL,
    DMA_Device_Sel_USB_RX2 = 17UL,
    DMA_Device_Sel_USB_TX3 = 18UL,
    DMA_Device_Sel_USB_RX3 = 18UL,
    DMA_Device_Sel_USB_TX4 = 19UL,
    DMA_Device_Sel_USB_RX4 = 19UL,
    DMA_Device_Sel_USB_TX5 = 20UL,
    DMA_Device_Sel_USB_RX5 = 20UL,
    DMA_Device_Sel_USB_TX6 = 21UL,
    DMA_Device_Sel_USB_RX6 = 21UL,
    DMA_Device_Sel_USB_TX7 = 22UL,
    DMA_Device_Sel_USB_RX7 = 22UL,
    DMA_Device_Sel_TIME0_RX = 24UL,
    DMA_Device_Sel_TIME1_RX = 25UL,
    DMA_Device_Sel_TIME2_RX = 26UL,
    DMA_Device_Sel_TIME3_RX = 27UL,
    DMA_Device_Sel_CAMERA_RX = 28UL,
    DMA_Device_Sel_UART3_TX = 29UL,
    DMA_Device_Sel_UART3_RX = 29UL,
} dma_device_select_t;

typedef enum
{
    DMA_Data_Width_8Bit = 0UL,
    DMA_Data_Width_16Bit = 1UL,
    DMA_Data_Width_24Bit = 2UL,
    DMA_Data_Width_32Bit = 3UL
} dma_data_width_t;

typedef enum
{
    DMA_Data_Location_Select_Low = 0UL,
    DMA_Data_Location_Select_High = 1UL,
} dma_data_location_select_t;

typedef enum
{
    DMA_Burst_Length_Burst1 = 0UL,
    DMA_Burst_Length_Burst2 = 1UL,
    DMA_Burst_Length_Burst4 = 2UL,
    DMA_Burst_Length_Burst8 = 3UL
} dma_burst_length_t;

typedef enum
{
    DMA_Address_Type_Fix = 0UL,
    DMA_Address_Type_Inc = 1UL,
} dma_addr_type_t;

typedef enum
{
    DMA_Address_Slave_Memory = 0UL,
    DMA_Address_Slave_Device = 1UL,
} dma_addr_slave_t;

typedef enum
{
    DMA_Dir_Memory_To_Memory         = 0UL,
    DMA_Dir_Memory_To_Peripheral     = 1UL,
    DMA_Dir_Peripheral_To_Memory     = 2UL,
    DMA_Dir_Peripheral_To_Peripheral = 3UL,
} dma_transfer_dir_t;


typedef enum
{
    DMA_Mode_Single = 0UL,
    DMA_Mode_Circular = 1UL,
} dma_mode_t;

typedef struct
{
    uint32_t src_start_addr;///<源地址
    uint32_t src_slot_offset;///<源数据存储形式中每个槽之间（头到头）的间距偏移 1-0x10000
    uint32_t src_word_offset;///<源数据在每个槽中的有效数据间（头到头）的间距偏移 1-0x10000
    uint32_t src_width;///<源数据搬运宽度    dma_data_width_t
    uint32_t src_dls;///<源地址设置，当src_width为24比特有效 dma_data_location_select_t
    uint32_t src_ifs;///<源地址选择，需要与src_start_addr相符合 dma_addr_type_t
    uint32_t src_burst_len;///<源每次搬运的长度 dma_burst_length_t
    uint32_t src_addr_type;///<源地址增长方式 dma_addr_type_t
    uint32_t src_slave;///<源数据存放的存储位置（memory或外设）dma_addr_slave_t

    uint32_t dst_start_addr;///<目的地址
    uint32_t dst_slot_offset;///<目的数据存储形式中每个槽之间（头到头）的间距偏移 1-0x10000
    uint32_t dst_word_offset;///<目的数据在每个槽中的有效数据间（头到头）的间距偏移 1-0x10000
    uint32_t dst_width;///<目的数据搬运宽度 dma_data_width_t
    uint32_t dst_dls;///<目的地址设置，当src_width为24比特有效 dma_data_location_select_t
    uint32_t dst_ifs;///<目的地址选择，需要与src_start_addr相符合 dma_addr_type_t
    uint32_t dst_burst_len;///<目的每次搬运的长度 dma_burst_length_t
    uint32_t dst_addr_type;///<目的地址增长方式 dma_addr_type_t
    uint32_t dst_slave;///<目的数据存放的存储位置（memory或外设）dma_addr_slave_t


    uint32_t slot_num;///<搬运总数据存储形式槽的数量，1-0x10000
    uint32_t byte_num;///<数据总数据存储形式槽中的数据数量，1-0x10000
    uint32_t priority;///<通道优先级，数值范围0-7，数据越大优先级越高
    uint32_t reload_en;///<重载使能 ENABLE DISABLE

} dma_config_parameter_t;


void DMA_Config(uint32_t channelx, dma_config_parameter_t *dma_config_struct);
void DMA_AccelerateCmd(uint32_t channelx, uint32_t state);
void DMA_Cmd(uint32_t channelx, uint32_t state);
uint32_t DMA_GetCmdStatus(uint32_t channelx);
void DMA_ITConfig(uint32_t channelx, uint32_t it_type, uint32_t state);
uint32_t DMA_GetITStatus(uint32_t channelx, uint32_t it_type);
void DMA_ClearITPendingBit(uint32_t channelx, uint32_t it_type);

void DMA_DMAPause(uint32_t channelx, uint32_t state);

void DMA_SetSourceAddr(uint32_t channelx, uint32_t addr);
uint32_t DMA_GetSourceAddr(uint32_t channelx);
void DMA_SetDestinationAddr(uint32_t channelx, uint32_t addr);
uint32_t DMA_GetDestinationAddr(uint32_t channelx);

void DMA_SetSourceBurstLength(uint32_t channelx, uint32_t BurstLength);
void DMA_SetDestinationBurstLength(uint32_t channelx, uint32_t BurstLength);

void DMA_SetSourceDataWidth(uint32_t channelx, uint32_t DataWidth);
void DMA_SetDestinationDataWidth(uint32_t channelx, uint32_t DataWidth);

void DMA_SetSourceSlotOffset(uint32_t channelx, uint32_t SlotOffset);
void DMA_SetSourceWordOffset(uint32_t channelx, uint32_t WordOffset);
void DMA_SetDestinationSlotOffset(uint32_t channelx, uint32_t SlotOffset);
void DMA_SetDestinationWordOffset(uint32_t channelx, uint32_t WordOffset);
void DMA_SetSlotNum(uint32_t channelx, uint32_t SlotNum);
uint16_t DMA_GetSlotNum(uint32_t channelx);
void DMA_SetByteNum(uint32_t channelx, uint32_t ByteNum);
uint16_t DMA_GetByteNum(uint32_t channelx);
#endif