#ifndef __DEV_SPIN_H__
#define __DEV_SPIN_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************SPI_CTL***********************************/
#define DEV_SPIn_CTL_LSB_MODE_MSB                               (0x0UL<<31)
#define DEV_SPIn_CTL_LSB_MODE_LSB                               (0x1UL<<31)
#define DEV_SPIn_CTL_LSB_MODE_MASK                              (0x1UL<<31)
#define DEV_SPIn_CTL_DIO_SWAP_DISABLE                           (0x0UL<<30)
#define DEV_SPIn_CTL_DIO_SWAP_ENABLE                            (0x1UL<<30)
#define DEV_SPIn_CTL_DIO_SWAP_MASK                              (0x1UL<<30)
#define DEV_SPIn_CTL_LOOP_BACK_NORMAL                           (0x0UL<<29)
#define DEV_SPIn_CTL_LOOP_BACK_INNERLOOPBACK                    (0x1UL<<29)
#define DEV_SPIn_CTL_LOOP_BACK_MASK                             (0x1UL<<29)
#define DEV_SPIn_CTL_RX_FIFO_THR_MASK                           (0x1fUL<<24)
#define DEV_SPIn_CTL_TX_FIFO_THR_MASK                           (0x1fUL<<19)
#define DEV_SPIn_CTL_RX_FIFO_RST_WORK                           (0x0UL<<18)
#define DEV_SPIn_CTL_RX_FIFO_RST_RESET                          (0x1UL<<18)
#define DEV_SPIn_CTL_RX_FIFO_RST_MASK                           (0x1UL<<18)
#define DEV_SPIn_CTL_TX_FIFO_RST_WORK                           (0x0UL<<17)
#define DEV_SPIn_CTL_TX_FIFO_RST_RESET                          (0x1UL<<17)
#define DEV_SPIn_CTL_TX_FIFO_RST_MASK                           (0x1UL<<17)
#define DEV_SPIn_CTL_DELAY_CHAIN_MASK                           (0x1fUL<<12)
#define DEV_SPIn_CTL_SPI_MODE_MODE0                             (0x0UL<<10)
#define DEV_SPIn_CTL_SPI_MODE_MODE1                             (0x1UL<<10)
#define DEV_SPIn_CTL_SPI_MODE_MODE2                             (0x2UL<<10)
#define DEV_SPIn_CTL_SPI_MODE_MODE3                             (0x3UL<<10)
#define DEV_SPIn_CTL_SPI_MODE_MASK                              (0x3UL<<10)
#define DEV_SPIn_CTL_MS_MODE_MASTER                             (0x0UL<<9)
#define DEV_SPIn_CTL_MS_MODE_SLAVE                              (0x1UL<<9)
#define DEV_SPIn_CTL_MS_MODE_MASK                               (0x1UL<<9)
#define DEV_SPIn_CTL_DIO_MODE_4WIRESPI                          (0x0UL<<8)
#define DEV_SPIn_CTL_DIO_MODE_3WIRESPI                          (0x1UL<<8)
#define DEV_SPIn_CTL_DIO_MODE_MASK                              (0x1UL<<8)
#define DEV_SPIn_CTL_SPI_WIDTH_SINGLE                           (0x0UL<<6)
#define DEV_SPIn_CTL_SPI_WIDTH_DUAL                             (0x1UL<<6)
#define DEV_SPIn_CTL_SPI_WIDTH_QUAD                             (0x2UL<<6)
#define DEV_SPIn_CTL_SPI_WIDTH_MASK                             (0x3UL<<6)
#define DEV_SPIn_CTL_CS_MODE_SOFTWARE                           (0x0UL<<4)
#define DEV_SPIn_CTL_CS_MODE_HARDWARE                           (0x1UL<<4)
#define DEV_SPIn_CTL_CS_MODE_MASK                               (0x1UL<<4)
#define DEV_SPIn_CTL_SPI_RX_EN_DISABLE                          (0x0UL<<3)
#define DEV_SPIn_CTL_SPI_RX_EN_ENABLE                           (0x1UL<<3)
#define DEV_SPIn_CTL_SPI_RX_EN_MASK                             (0x1UL<<3)
#define DEV_SPIn_CTL_SPI_TX_EN_DISABLE                          (0x0UL<<2)
#define DEV_SPIn_CTL_SPI_TX_EN_ENABLE                           (0x1UL<<2)
#define DEV_SPIn_CTL_SPI_TX_EN_MASK                             (0x1UL<<2)
#define DEV_SPIn_CTL_SPI_CS_NSSHIGH                             (0x0UL<<1)
#define DEV_SPIn_CTL_SPI_CS_NSSLOW                              (0x1UL<<1)
#define DEV_SPIn_CTL_SPI_CS_MASK                                (0x1UL<<1)
#define DEV_SPIn_CTL_SPI_EN_DISABLE                             (0x0UL<<0)
#define DEV_SPIn_CTL_SPI_EN_ENABLE                              (0x1UL<<0)
#define DEV_SPIn_CTL_SPI_EN_MASK                                (0x1UL<<0)
/****SPI_CTL end****/


/***********************************SPI_STA***********************************/
#define DEV_SPIn_STA_RX_EMPTY                                   (0x1UL<<30)
#define DEV_SPIn_STA_RX_FULL                                    (0x1UL<<29)
#define DEV_SPIn_STA_RX_LEVEL_MASK                              (0x1fUL<<24)
#define DEV_SPIn_STA_TX_EMPTY                                   (0x1UL<<22)
#define DEV_SPIn_STA_TX_FULL                                    (0x1UL<<21)
#define DEV_SPIn_STA_TX_LEVEL_MASK                              (0x1fUL<<16)
#define DEV_SPIn_STA_SPI_IDLE_SPIBUSY                           (0x0UL<<8)
#define DEV_SPIn_STA_SPI_IDLE_SPIIDLE                           (0x1UL<<8)
#define DEV_SPIn_STA_SPI_IDLE_MASK                              (0x1UL<<8)
#define DEV_SPIn_STA_SPI_WORK_STOP                              (0x0UL<<0)
#define DEV_SPIn_STA_SPI_WORK_WORKED                            (0x1UL<<0)
#define DEV_SPIn_STA_SPI_WORK_MASK                              (0x1UL<<0)
/****SPI_STA end****/


/***********************************SPI_RX_NUM***********************************/
#define DEV_SPIn_RX_NUM_RX_START                                (0x1UL<<24)
#define DEV_SPIn_RX_NUM_MASK                                    (0xffffffUL<<0)
/****SPI_RX_NUM end****/


/***********************************SPI_RX_CNT***********************************/
#define DEV_SPIn_RX_CNT_MASK                                    (0xffffffUL<<0)
/****SPI_RX_CNT end****/


/***********************************SPI_TX_DATA***********************************/
#define DEV_SPIn_TX_DATA_MASK                                   (0xffUL<<0)
/****SPI_TX_DATA end****/


/***********************************SPI_RX_DATA***********************************/
#define DEV_SPIn_RX_DATA_MASK                                   (0xffUL<<0)
/****SPI_RX_DATA end****/


/***********************************SPI_PD***********************************/
#define DEV_SPIn_PD_RX_OF                                       (0x1UL<<7)
#define DEV_SPIn_PD_TX_UF                                       (0x1UL<<6)
#define DEV_SPIn_PD_RX_END                                      (0x1UL<<5)
#define DEV_SPIn_PD_TX_END                                      (0x1UL<<4)
#define DEV_SPIn_PD_RX_UF                                       (0x1UL<<3)
#define DEV_SPIn_PD_TX_OF                                       (0x1UL<<2)
#define DEV_SPIn_PD_RX_THR                                      (0x1UL<<1)
#define DEV_SPIn_PD_TX_THR                                      (0x1UL<<0)
/****SPI_PD end****/


/***********************************SPI_IE***********************************/
#define DEV_SPIn_IE_RX_DMA_EN                                   (0x1UL<<17)
#define DEV_SPIn_IE_TX_DMA_EN                                   (0x1UL<<16)
#define DEV_SPIn_IE_RX_OF                                       (0x1UL<<7)
#define DEV_SPIn_IE_TX_UF                                       (0x1UL<<6)
#define DEV_SPIn_IE_RX_END                                      (0x1UL<<5)
#define DEV_SPIn_IE_TX_END                                      (0x1UL<<4)
#define DEV_SPIn_IE_RX_UF                                       (0x1UL<<3)
#define DEV_SPIn_IE_TX_OF                                       (0x1UL<<2)
#define DEV_SPIn_IE_RX_THR                                      (0x1UL<<1)
#define DEV_SPIn_IE_TX_THR                                      (0x1UL<<0)
/****SPI_IE end****/


/***********************************DEV_SPIn register***********************************/
typedef struct
{

    __IO    uint32_t    CTL;                                     /* 0x0    SPI Control */
    __IO    uint32_t    STA;                                     /* 0x4    SPI STATUS */
    __IO    uint32_t    RX_NUM;                                  /* 0x8    RX Number */
    __I     uint32_t    RX_CNT;                                  /* 0xc    RX Counter */
    __IO    uint32_t    TX_DATA;                                 /* 0x10    TX Data(FIFO) */
    __I     uint32_t    RX_DATA;                                 /* 0x14    RX Data(FIFO) */
    uint32_t    RESERVED0[2];
    __IO    uint32_t    PD;                                      /* 0x20    SPI Pending */
    __IO    uint32_t    IE;                                      /* 0x24    SPI Interrupt Enable */
} DEV_SPIn_RegDef;
/****DEV_SPIn end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
