#ifndef __DEV_UARTN_H__
#define __DEV_UARTN_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************UART_CFG***********************************/
#define DEV_UARTn_CFG_TO_DIV(_total_)                           (((_total_)-1)<<20)
#define DEV_UARTn_CFG_TO_DIV_MASK                               (0x3fUL<<20)
#define DEV_UARTn_CFG_RTS_WORK                                  (0x0UL<<17)
#define DEV_UARTn_CFG_RTS_STOP                                  (0x1UL<<17)
#define DEV_UARTn_CFG_RTS_MASK                                  (0x1UL<<17)
#define DEV_UARTn_CFG_AFC_DISABLE                               (0x0UL<<16)
#define DEV_UARTn_CFG_AFC_ENABLE                                (0x1UL<<16)
#define DEV_UARTn_CFG_AFC_MASK                                  (0x1UL<<16)
#define DEV_UARTn_CFG_RX_FIFO_THR_MASK                          (0xfUL<<12)
#define DEV_UARTn_CFG_TX_FIFO_THR_MASK                          (0xfUL<<8)
#define DEV_UARTn_CFG_PARITY_SEL_EVEN_PARITY                    (0x0UL<<6)
#define DEV_UARTn_CFG_PARITY_SEL_ODD_PARITY                     (0x1UL<<6)
#define DEV_UARTn_CFG_PARITY_SEL_FORCE0                         (0x2UL<<6)
#define DEV_UARTn_CFG_PARITY_SEL_FORCE1                         (0x3UL<<6)
#define DEV_UARTn_CFG_PARITY_SEL_MASK                           (0x3UL<<6)
#define DEV_UARTn_CFG_PARITY_EN_DISABLE                         (0x0UL<<4)
#define DEV_UARTn_CFG_PARITY_EN_ENABLE                          (0x1UL<<4)
#define DEV_UARTn_CFG_PARITY_EN_MASK                            (0x1UL<<4)
#define DEV_UARTn_CFG_LOOPBACK_EN_DISABLE                       (0x0UL<<3)
#define DEV_UARTn_CFG_LOOPBACK_EN_ENABLE                        (0x1UL<<3)
#define DEV_UARTn_CFG_LOOPBACK_EN_MASK                          (0x1UL<<3)
#define DEV_UARTn_CFG_STOP_BIT_1BIT                             (0x0UL<<2)
#define DEV_UARTn_CFG_STOP_BIT_2BIT                             (0x1UL<<2)
#define DEV_UARTn_CFG_STOP_BIT_MASK                             (0x1UL<<2)
#define DEV_UARTn_CFG_DATA_WIDTH_5BIT                           (0x0UL<<0)
#define DEV_UARTn_CFG_DATA_WIDTH_6BIT                           (0x1UL<<0)
#define DEV_UARTn_CFG_DATA_WIDTH_7BIT                           (0x2UL<<0)
#define DEV_UARTn_CFG_DATA_WIDTH_8BIT                           (0x3UL<<0)
#define DEV_UARTn_CFG_DATA_WIDTH_MASK                           (0x3UL<<0)
/****UART_CFG end****/


/***********************************UART_DIV***********************************/
#define DEV_UARTn_DIV_RX_DIV(clock,baud_rate)                   ((((clock)/(baud_rate))-1)<<16)
#define DEV_UARTn_DIV_RX_DIV_MASK                               (0xffffUL<<16)
#define DEV_UARTn_DIV_TX_DIV(clock,baud_rate)                   ((((clock)/(baud_rate))-1)<<0)
#define DEV_UARTn_DIV_TX_DIV_MASK                               (0xffffUL<<0)
/****UART_DIV end****/


/***********************************UART_CTL***********************************/
#define DEV_UARTn_CTL_ABD_DISABLE                               (0x0UL<<6)
#define DEV_UARTn_CTL_ABD_ENABLE                                (0x1UL<<6)
#define DEV_UARTn_CTL_ABD_MASK                                  (0x1UL<<6)
#define DEV_UARTn_CTL_RX_FIFO_RST_DISABLE                       (0x0UL<<5)
#define DEV_UARTn_CTL_RX_FIFO_RST_ENABLE                        (0x1UL<<5)
#define DEV_UARTn_CTL_RX_FIFO_RST_MASK                          (0x1UL<<5)
#define DEV_UARTn_CTL_TX_FIFO_RST_DISABLE                       (0x0UL<<4)
#define DEV_UARTn_CTL_TX_FIFO_RST_ENABLE                        (0x1UL<<4)
#define DEV_UARTn_CTL_TX_FIFO_RST_MASK                          (0x1UL<<4)
#define DEV_UARTn_CTL_RX_DMA_EN_DISABLE                         (0x0UL<<3)
#define DEV_UARTn_CTL_RX_DMA_EN_ENABLE                          (0x1UL<<3)
#define DEV_UARTn_CTL_RX_DMA_EN_MASK                            (0x1UL<<3)
#define DEV_UARTn_CTL_TX_DMA_EN_DISABLE                         (0x0UL<<2)
#define DEV_UARTn_CTL_TX_DMA_EN_ENABLE                          (0x1UL<<2)
#define DEV_UARTn_CTL_TX_DMA_EN_MASK                            (0x1UL<<2)
#define DEV_UARTn_CTL_RX_EN_DISABLE                             (0x0UL<<1)
#define DEV_UARTn_CTL_RX_EN_ENABLE                              (0x1UL<<1)
#define DEV_UARTn_CTL_RX_EN_MASK                                (0x1UL<<1)
#define DEV_UARTn_CTL_TX_EN_DISABLE                             (0x0UL<<0)
#define DEV_UARTn_CTL_TX_EN_ENABLE                              (0x1UL<<0)
#define DEV_UARTn_CTL_TX_EN_MASK                                (0x1UL<<0)
/****UART_CTL end****/


/***********************************UART_IE***********************************/
#define DEV_UARTn_IE_TX_END                                     (0x1UL<<9)
#define DEV_UARTn_IE_DET_END                                    (0x1UL<<8)
#define DEV_UARTn_IE_TIME_OUT                                   (0x1UL<<7)
#define DEV_UARTn_IE_PARITY_ERR                                 (0x1UL<<6)
#define DEV_UARTn_IE_FRAME_ERR                                  (0x1UL<<5)
#define DEV_UARTn_IE_RX_FIFO_UF                                 (0x1UL<<4)
#define DEV_UARTn_IE_RX_FIFO_OF                                 (0x1UL<<3)
#define DEV_UARTn_IE_TX_FIFO_OF                                 (0x1UL<<2)
#define DEV_UARTn_IE_RX_FIFO_THR                                (0x1UL<<1)
#define DEV_UARTn_IE_TX_FIFO_THR                                (0x1UL<<0)
/****UART_IE end****/


/***********************************UART_PD***********************************/
#define DEV_UARTn_PD_TX_END                                     (0x1UL<<9)
#define DEV_UARTn_PD_DET_END                                    (0x1UL<<8)
#define DEV_UARTn_PD_TIME_OUT                                   (0x1UL<<7)
#define DEV_UARTn_PD_PARITY_ERR                                 (0x1UL<<6)
#define DEV_UARTn_PD_FRAME_ERR                                  (0x1UL<<5)
#define DEV_UARTn_PD_RX_FIFO_UF                                 (0x1UL<<4)
#define DEV_UARTn_PD_RX_FIFO_OF                                 (0x1UL<<3)
#define DEV_UARTn_PD_TX_FIFO_OF                                 (0x1UL<<2)
#define DEV_UARTn_PD_RX_FIFO_THR                                (0x1UL<<1)
#define DEV_UARTn_PD_TX_FIFO_THR                                (0x1UL<<0)
/****UART_PD end****/


/***********************************UART_STA***********************************/
#define DEV_UARTn_STA_CTS                                       (0x1UL<<16)
#define DEV_UARTn_STA_RX_BUSY                                   (0x1UL<<15)
#define DEV_UARTn_STA_RX_FIFO_FULL                              (0x1UL<<14)
#define DEV_UARTn_STA_RX_FIFO_EMPTY                             (0x1UL<<13)
#define DEV_UARTn_STA_RX_FIFO_RLVL_MASK                         (0x1fUL<<8)
#define DEV_UARTn_STA_TX_BUSY                                   (0x1UL<<7)
#define DEV_UARTn_STA_TX_FIFO_FULL                              (0x1UL<<6)
#define DEV_UARTn_STA_TX_FIFO_EMPTY                             (0x1UL<<5)
#define DEV_UARTn_STA_TX_FIFO_WLVL_MASK                         (0x1fUL<<0)
/****UART_STA end****/


/***********************************UART_RX_CNT***********************************/
#define DEV_UARTn_RX_CNT_MASK                                   (0xffffUL<<0)
/****UART_RX_CNT end****/


/***********************************UART_TX_DAT***********************************/
#define DEV_UARTn_TX_DAT_MASK                                   (0xffUL<<0)
/****UART_TX_DAT end****/


/***********************************UART_RX_DAT***********************************/
#define DEV_UARTn_RX_DAT_MASK                                   (0xffUL<<0)
/****UART_RX_DAT end****/


/***********************************DEV_UARTn register***********************************/
typedef struct
{
    __IO    uint32_t    CFG;                                     /* 0x0    UART Configure */
    __IO    uint32_t    DIV;                                     /* 0x4    UART Divide */
    uint32_t    RESERVED0;
    __IO    uint32_t    CTL;                                     /* 0xc    UART Control */
    __IO    uint32_t    IE;                                      /* 0x10    UART Interrupt Enable */
    __IO    uint32_t    PD;                                      /* 0x14    UART Interrupt Pending */
    __I     uint32_t    STA;                                     /* 0x18    UART Status */
    __I     uint32_t    RX_CNT;                                  /* 0x1c    UART Rx Counter
(used for Auto Baud Rate Detect) */
    __IO    uint32_t    TX_DAT;                                  /* 0x20    UART Tx Data(FIFO) */
    __IO    uint32_t    RX_DAT;                                  /* 0x24    UART Rx Data(FIFO) */
} DEV_UARTn_RegDef;
/****DEV_UARTn end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
