#ifndef __AON_OSC_H__
#define __AON_OSC_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************OSC_DEV_CTL***********************************/
#define AON_OSC_DEV_CTL_DEV_EN                                  (0x1UL<<0)
/****OSC_DEV_CTL end****/


/***********************************OSC_XTAL_CTL***********************************/
#define AON_OSC_XTAL_CTL_TESTEN                                 (0x1UL<<27)
#define AON_OSC_XTAL_CTL_DEBEN                                  (0x1UL<<26)
#define AON_OSC_XTAL_CTL_ICAPF_MASK                             (0x1fUL<<21)
#define AON_OSC_XTAL_CTL_ICAPC_MASK                             (0xfUL<<17)
#define AON_OSC_XTAL_CTL_OCAPF_MASK                             (0x1fUL<<12)
#define AON_OSC_XTAL_CTL_OCAPC_MASK                             (0xfUL<<8)
#define AON_OSC_XTAL_CTL_GMCTL_MASK                             (0xfUL<<4)
#define AON_OSC_XTAL_CTL_BUFSEL_SHMITTEROUTPUT                  (0x0UL<<2)
#define AON_OSC_XTAL_CTL_BUFSEL_BUFFEROUTPUT                    (0x1UL<<2)
#define AON_OSC_XTAL_CTL_BUFSEL_MASK                            (0x1UL<<2)
#define AON_OSC_XTAL_CTL_CAPON                                  (0x1UL<<1)
#define AON_OSC_XTAL_CTL_EN                                     (0x1UL<<0)
/****OSC_XTAL_CTL end****/


/***********************************OSC_TRIM***********************************/
#define AON_OSC_TRIM_AUDIO_PLL_TRIM_MASK                        (0xfUL<<16)
#define AON_OSC_TRIM_DEV_TRIM_037_941395MHZ                     (0x0UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_037_158404MHZ                     (0x1UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_037_087001MHZ                     (0x2UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_036_384888MHZ                     (0x3UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_036_315848MHZ                     (0x4UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_035_652451MHZ                     (0x5UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_035_582440MHZ                     (0x6UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_034_955563MHZ                     (0x7UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_034_890314MHZ                     (0x8UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_034_297596MHZ                     (0x9UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_034_233606MHZ                     (0xaUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_033_670742MHZ                     (0xbUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_033_610974MHZ                     (0xcUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_033_076371MHZ                     (0xdUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_033_014809MHZ                     (0xeUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_032_508696MHZ                     (0xfUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_032_453374MHZ                     (0x10UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_031_971034MHZ                     (0x11UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_031_917525MHZ                     (0x12UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_031_457484MHZ                     (0x13UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_031_409131MHZ                     (0x14UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_030_967722MHZ                     (0x15UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_030_918293MHZ                     (0x16UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_030_497975MHZ                     (0x17UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_030_451481MHZ                     (0x18UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_030_050165MHZ                     (0x19UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_030_007952MHZ                     (0x1aUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_029_624308MHZ                     (0x1bUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_029_582353MHZ                     (0x1cUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_029_216380MHZ                     (0x1dUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_029_176689MHZ                     (0x1eUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_028_826128MHZ                     (0x1fUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_028_795882MHZ                     (0x20UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_028_460889MHZ                     (0x21UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_028_420950MHZ                     (0x22UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_028_100791MHZ                     (0x23UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_028_065350MHZ                     (0x24UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_027_756190MHZ                     (0x25UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_027_724110MHZ                     (0x26UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_027_422147MHZ                     (0x27UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_027_397401MHZ                     (0x28UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_027_107709MHZ                     (0x29UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_027_081144MHZ                     (0x2aUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_026_802960MHZ                     (0x2bUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_026_775106MHZ                     (0x2cUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_026_511881MHZ                     (0x2dUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_026_481254MHZ                     (0x2eUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_026_224951MHZ                     (0x2fUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_026_198971MHZ                     (0x30UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_025_951150MHZ                     (0x31UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_025_928525MHZ                     (0x32UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_025_690059MHZ                     (0x33UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_025_666404MHZ                     (0x34UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_025_434088MHZ                     (0x35UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_025_415221MHZ                     (0x36UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_025_190583MHZ                     (0x37UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_025_173263MHZ                     (0x38UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_024_955198MHZ                     (0x39UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_024_937189MHZ                     (0x3aUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_024_725814MHZ                     (0x3bUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_024_712333MHZ                     (0x3cUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_024_506163MHZ                     (0x3dUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_024_494232MHZ                     (0x3eUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_024_294621MHZ                     (0x3fUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_024_308573MHZ                     (0x40UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_024_117016MHZ                     (0x41UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_024_105679MHZ                     (0x42UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_023_916221MHZ                     (0x43UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_023_900109MHZ                     (0x44UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_023_718954MHZ                     (0x45UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_023_703809MHZ                     (0x46UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_023_530588MHZ                     (0x47UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_023_520107MHZ                     (0x48UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_023_345157MHZ                     (0x49UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_023_335725MHZ                     (0x4aUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_023_166951MHZ                     (0x4bUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_023_157294MHZ                     (0x4cUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_998915MHZ                     (0x4dUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_990554MHZ                     (0x4eUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_837829MHZ                     (0x4fUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_827500MHZ                     (0x50UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_680301MHZ                     (0x51UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_664976MHZ                     (0x52UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_516342MHZ                     (0x53UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_501427MHZ                     (0x54UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_365704MHZ                     (0x55UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_358547MHZ                     (0x56UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_211055MHZ                     (0x57UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_208311MHZ                     (0x58UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_069087MHZ                     (0x59UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_022_061602MHZ                     (0x5aUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_931478MHZ                     (0x5bUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_921412MHZ                     (0x5cUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_798425MHZ                     (0x5dUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_784594MHZ                     (0x5eUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_660171MHZ                     (0x5fUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_650850MHZ                     (0x60UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_528612MHZ                     (0x61UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_516539MHZ                     (0x62UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_398613MHZ                     (0x63UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_379799MHZ                     (0x64UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_258080MHZ                     (0x65UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_262741MHZ                     (0x66UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_139666MHZ                     (0x67UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_141034MHZ                     (0x68UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_023475MHZ                     (0x69UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_021_009728MHZ                     (0x6aUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_901672MHZ                     (0x6bUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_893975MHZ                     (0x6cUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_777629MHZ                     (0x6dUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_773987MHZ                     (0x6eUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_666174MHZ                     (0x6fUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_664893MHZ                     (0x70UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_554615MHZ                     (0x71UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_551315MHZ                     (0x72UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_435558MHZ                     (0x73UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_440023MHZ                     (0x74UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_332539MHZ                     (0x75UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_330498MHZ                     (0x76UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_232343MHZ                     (0x77UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_225463MHZ                     (0x78UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_130876MHZ                     (0x79UL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_120573MHZ                     (0x7aUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_022550MHZ                     (0x7bUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_020_026836MHZ                     (0x7cUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_019_923395MHZ                     (0x7dUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_019_923419MHZ                     (0x7eUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_019_826321MHZ                     (0x7fUL<<8)
#define AON_OSC_TRIM_DEV_TRIM_MASK                              (0x7fUL<<8)
#define AON_OSC_TRIM_ADC_TRIM_355_301KHZ                        (0x0UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_358_458KHZ                        (0x1UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_361_874KHZ                        (0x2UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_365_168KHZ                        (0x3UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_368_719KHZ                        (0x4UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_372_119KHZ                        (0x5UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_375_800KHZ                        (0x6UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_379_356KHZ                        (0x7UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_383_167KHZ                        (0x8UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_386_848KHZ                        (0x9UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_390_845KHZ                        (0xaUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_394_670KHZ                        (0xbUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_398_822KHZ                        (0xcUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_402_822KHZ                        (0xdUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_407_152KHZ                        (0xeUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_411_340KHZ                        (0xfUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_416_901KHZ                        (0x10UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_421_270KHZ                        (0x11UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_425_970KHZ                        (0x12UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_430_565KHZ                        (0x13UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_435_528KHZ                        (0x14UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_440_315KHZ                        (0x15UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_445_497KHZ                        (0x16UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_450_522KHZ                        (0x17UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_455_950KHZ                        (0x18UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_461_195KHZ                        (0x19UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_466_864KHZ                        (0x1aUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_472_384KHZ                        (0x1bUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_478_380KHZ                        (0x1cUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_484_143KHZ                        (0x1dUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_490_440KHZ                        (0x1eUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_496_540KHZ                        (0x1fUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_506_237KHZ                        (0x20UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_512_740KHZ                        (0x21UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_519_774KHZ                        (0x22UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_526_629KHZ                        (0x23UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_534_054KHZ                        (0x24UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_541_323KHZ                        (0x25UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_549_180KHZ                        (0x26UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_556_867KHZ                        (0x27UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_565_196KHZ                        (0x28UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_573_301KHZ                        (0x29UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_582_166KHZ                        (0x2aUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_590_782KHZ                        (0x2bUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_600_179KHZ                        (0x2cUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_609_339KHZ                        (0x2dUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_619_396KHZ                        (0x2eUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_629_184KHZ                        (0x2fUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_642_390KHZ                        (0x30UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_652_888KHZ                        (0x31UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_664_409KHZ                        (0x32UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_675_738KHZ                        (0x33UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_688_125KHZ                        (0x34UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_700_216KHZ                        (0x35UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_713_543KHZ                        (0x36UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_726_674KHZ                        (0x37UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_741_045KHZ                        (0x38UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_755_168KHZ                        (0x39UL<<0)
#define AON_OSC_TRIM_ADC_TRIM_770_734KHZ                        (0x3aUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_786_010KHZ                        (0x3bUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_802_895KHZ                        (0x3cUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_819_556KHZ                        (0x3dUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_837_986KHZ                        (0x3eUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_856_067KHZ                        (0x3fUL<<0)
#define AON_OSC_TRIM_ADC_TRIM_MASK                              (0x3fUL<<0)
/****OSC_TRIM end****/


/***********************************OSC_TEST***********************************/
#define AON_OSC_TEST_ATEST_SEL_AUDIO_PLLTEST                    (0x0UL<<8)
#define AON_OSC_TEST_ATEST_SEL_CORE_PLLTEST                     (0x1UL<<8)
#define AON_OSC_TEST_ATEST_SEL_MASK                             (0x1UL<<8)
#define AON_OSC_TEST_DTEST_EN_ANALOGTESTOUTPUT                  (0x0UL<<7)
#define AON_OSC_TEST_DTEST_EN_DIGITALTESTOUTPUT                 (0x1UL<<7)
#define AON_OSC_TEST_DTEST_EN_MASK                              (0x1UL<<7)
#define AON_OSC_TEST_DTEST_DIV_FORBIDDEN0                       (0x0UL<<4)
#define AON_OSC_TEST_DTEST_DIV_1                                (0x1UL<<4)
#define AON_OSC_TEST_DTEST_DIV_FORBIDDEN1                       (0x2UL<<4)
#define AON_OSC_TEST_DTEST_DIV_MASK                             (0x7UL<<4)
#define AON_OSC_TEST_DTEST_SEL_0                                (0x0UL<<1)
#define AON_OSC_TEST_DTEST_SEL_CKO_XTAL                         (0x1UL<<1)
#define AON_OSC_TEST_DTEST_SEL_CKO_CORE_PLL                     (0x2UL<<1)
#define AON_OSC_TEST_DTEST_SEL_CKO_OSC_DEV                      (0x3UL<<1)
#define AON_OSC_TEST_DTEST_SEL_1                                (0x4UL<<1)
#define AON_OSC_TEST_DTEST_SEL_CKO_OSC_AUDIO                    (0x5UL<<1)
#define AON_OSC_TEST_DTEST_SEL_MASK                             (0x7UL<<1)
#define AON_OSC_TEST_TEST_EN_DISABLE                            (0x0UL<<0)
#define AON_OSC_TEST_TEST_EN_ENABLE                             (0x1UL<<0)
#define AON_OSC_TEST_TEST_EN_MASK                               (0x1UL<<0)
/****OSC_TEST end****/


/***********************************AON_OSC register***********************************/
typedef struct
{
    __IO    uint32_t    DEV_CTL;                                 /* 0x0    OSC Device Clock Control(24M) */
    __IO    uint32_t    XTAL_CTL;                                /* 0x4    OSC XTAL Clock Control(24M) */
    uint32_t    RESERVED0[2];
    __IO    uint32_t    TRIM;                                    /* 0x10    OSC Trim */
    __IO    uint32_t    TEST;                                    /* 0x14    OSC Test */
} AON_OSC_RegDef;
/****AON_OSC end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
