/*
 * Copyright (c) 2012-2019 Andes Technology Corporation
 * All rights reserved.
 *
 */

#ifndef __SPV40_H__
#define __SPV40_H__

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 * Clock-related Definitions
 ******************************************************************************/
#define KHz                     1000
#define MHz                     1000000

#define US						1
#define MS						1000

/*******************************************************************************
 * PLIC (NCEPLIC100 IP) Interrupt Source Definition
 * Global interrupt sources are assigned small unsigned integer identifiers,
 * beginning at 1. An interrupt ID of 0 is reserved to mean 'no interrupt'.
 * IDs are also used to break ties when two or more interrupt sources have the
 * same assigned priority: Smaller values of ID take precedence over larger
 * values of ID.
 ******************************************************************************/
#define    IRQ_SOURCE_WDOG     	1
#define    IRQ_SOURCE_PMU      	2
#define    IRQ_SOURCE_LRADC    	3
#define    IRQ_SOURCE_ADUI     	4
#define    IRQ_SOURCE_UDSP     	5
#define    IRQ_SOURCE_NPU_TAB  	6
#define    IRQ_SOURCE_NPU_RES  	7
#define    IRQ_SOURCE_TIMER0   	8
#define    IRQ_SOURCE_TIMER1   	9
#define    IRQ_SOURCE_TIMER2   	10
#define    IRQ_SOURCE_TIMER3   	11
#define    IRQ_SOURCE_CAPTURE0 	12
#define    IRQ_SOURCE_CAPTURE1 	13
#define    IRQ_SOURCE_CAPTURE2 	14
#define    IRQ_SOURCE_CAPTURE3 	15
#define    IRQ_SOURCE_IRRX     	16
#define    IRQ_SOURCE_IRTX     	17
#define    IRQ_SOURCE_SPI0     	18
#define    IRQ_SOURCE_SPI1     	19
#define    IRQ_SOURCE_SDC      	20
#define    IRQ_SOURCE_ADC      	21
#define    IRQ_SOURCE_DAC      	22
#define    IRQ_SOURCE_SRC      	23
#define    IRQ_SOURCE_DMA      	24
#define    IRQ_SOURCE_MMU      	25
#define    IRQ_SOURCE_NORC     	26
#define    IRQ_SOURCE_UART0    	27
#define    IRQ_SOURCE_UART1    	28
#define    IRQ_SOURCE_UART2    	29
#define    IRQ_SOURCE_I2C0     	30
#define    IRQ_SOURCE_I2C1     	31
#define    IRQ_SOURCE_ASI0     	32
#define    IRQ_SOURCE_ASI1     	33
#define    IRQ_SOURCE_USB_MAC  	34
#define    IRQ_SOURCE_USB_DMA  	35
#define    IRQ_SOURCE_GPIO0    	36
#define    IRQ_SOURCE_GPIO1    	37
#define    IRQ_SOURCE_PWM      	38
#define    IRQ_SOURCE_CAMERA   	39
#define    IRQ_SOURCE_UART3    	40
#define    IRQ_SOURCE_PSRAM    	41
#define    IRQ_SOURCE_MPU      	42

/*******************************************************************************
 * SPV40 Memory Region / Memory-mapped Peripheral Description
 ******************************************************************************/

#define    _IO_(addr)              (addr)
#define    PLIC_BASE               _IO_(0x10000000)
#define    PLMT_BASE               _IO_(0x12000000)
#define    PLIC_SW_BASE            _IO_(0x12400000)
#define    PLDM_BASE               _IO_(0x12800000)

#define    CPU_ILM_BASE            _IO_(0x00000000)
#define    CPU_DLM_BASE            _IO_(0x00100000)
#define    CODE_SRAM_L1C_BASE      _IO_(0x40000000)
#define    CODE_ILM_L1C_BASE       _IO_(0x41000000)
#define    CODE_DLM_L1C_BASE       _IO_(0x41100000)
#define    CODE_AON_L1C_BASE       _IO_(0x42000000)
#define    CODE_L2C_L1C_BASE       _IO_(0x48000000)
#define    CODE_L2N_L1C_BASE       _IO_(0x4C000000)
#define    DATA_SRAM_L1C_BASE      _IO_(0x50000000)
#define    DATA_ILM_L1C_BASE       _IO_(0x51000000)
#define    DATA_DLM_L1C_BASE       _IO_(0x51100000)
#define    DATA_AON_L1C_BASE       _IO_(0x52000000)
#define    DATA_L2C_L1C_BASE       _IO_(0x58000000)
#define    DATA_L2N_L1C_BASE       _IO_(0x5C000000)
#define    CODE_SRAM_L1N_BASE      _IO_(0x60000000)
#define    CODE_ILM_L1N_BASE       _IO_(0x61000000)
#define    CODE_DLM_L1N_BASE       _IO_(0x61100000)
#define    CODE_AON_L1N_BASE       _IO_(0x62000000)
#define    CODE_L2C_L1N_BASE       _IO_(0x68000000)
#define    CODE_L2N_L1N_BASE       _IO_(0x6C000000)
#define    DATA_SRAM_L1N_BASE      _IO_(0x70000000)
#define    DATA_ILM_L1N_BASE       _IO_(0x71000000)
#define    DATA_DLM_L1N_BASE       _IO_(0x71100000)
#define    DATA_AON_L1N_BASE       _IO_(0x72000000)
#define    DATA_L2C_L1N_BASE       _IO_(0x78000000)
#define    DATA_L2N_L1N_BASE       _IO_(0x7C000000)

#define    CPU_ILM_SIZE            0x00010000
#define    CPU_DLM_SIZE            0x00040000
#define    CODE_SRAM_L1C_SIZE      0x00040000
#define    CODE_ILM_L1C_SIZE       0x00010000
#define    CODE_DLM_L1C_SIZE       0x00040000
#define    CODE_AON_L1C_SIZE       0x00001000
#define    CODE_L2C_L1C_SIZE       0x01000000
#define    CODE_L2N_L1C_SIZE       0x01000000
#define    DATA_SRAM_L1C_SIZE      0x00040000
#define    DATA_ILM_L1C_SIZE       0x00010000
#define    DATA_DLM_L1C_SIZE       0x00040000
#define    DATA_AON_L1C_SIZE       0x00001000
#define    DATA_L2C_L1C_SIZE       0x01000000
#define    DATA_L2N_L1C_SIZE       0x01000000
#define    CODE_SRAM_L1N_SIZE      0x00040000
#define    CODE_ILM_L1N_SIZE       0x00010000
#define    CODE_DLM_L1N_SIZE       0x00040000
#define    CODE_AON_L1N_SIZE       0x00001000
#define    CODE_L2C_L1N_SIZE       0x01000000
#define    CODE_L2N_L1N_SIZE       0x01000000
#define    DATA_SRAM_L1N_SIZE      0x00040000
#define    DATA_ILM_L1N_SIZE       0x00010000
#define    DATA_DLM_L1N_SIZE       0x00040000
#define    DATA_AON_L1N_SIZE       0x00001000
#define    DATA_L2C_L1N_SIZE       0x01000000
#define    DATA_L2N_L1N_SIZE       0x01000000



#ifndef __ASSEMBLER__

#define __I                     volatile const	/* 'read only' permissions    */
#define __O                     volatile        /* 'write only' permissions   */
#define __IO                    volatile        /* 'read / write' permissions */

/*******************************************************************************
 * Global Data For Essential SoC Configurations
 ******************************************************************************/

typedef enum
{
	DISABLE,
	ENABLE
} Options_EnableEnum;

typedef enum
{
	RESET = 0UL,
	SET = 1UL
} Options_StateEnum;

typedef enum
{
	OFF = 0UL,
	ON	= 1UL
} Options_SwitchEnum;

/**
 * @brief
 * @details
 */
typedef struct {
	__IO uint32_t MTIME_Period_Counts;
	__IO uint32_t Sys_Ticks;
	__IO uint32_t Delay_Cycle_Timebase;
} SOC_RUNTIME;

/*****************************************************************************
 * PLMT - Machine Timer Unit (NCEPLMT100)
 ****************************************************************************/
typedef struct {
	__IO uint32_t MTIME_L; /* 0x00 Machine Time (L)*/
	__IO uint32_t MTIME_H; /* 0x04 Machine Time (H)*/
	__IO uint32_t MTIMECMP_L; /* 0x08 Machine Time Compare (L)*/
	__IO uint32_t MTIMECMP_H; /* 0x0c Machine Time Compare (H)*/
} PLMT_RegDef;

/*****************************************************************************
 * D25F CPU Core Device Declaration
 ****************************************************************************/
#define 	DEV_MTIME              ((PLMT_RegDef *) PLMT_BASE)

#endif	/* __ASSEMBLER__ */

#ifdef __cplusplus
}
#endif

#endif	/* __SPV40_H__ */
