#ifndef __DEV_PWM_H__
#define __DEV_PWM_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************PWMn_CTL***********************************/
#define DEV_PWM_CTL_DutyMode_NUM_MASK                           (0x3fUL<<26)
#define DEV_PWM_CTL_DutyMode_CLK_OUT                            (0x1UL<<25)
#define DEV_PWM_CTL_DutyMode_DUTY_MASK                          (0x1ffUL<<16)
#define DEV_PWM_CTL_DutyMode_LEN(total_cycle)                   (((total_cycle)-1)<<8)
#define DEV_PWM_CTL_DutyMode_LEN_MASK                           (0xffUL<<8)
#define DEV_PWM_CTL_DutyMode_MODE_NORMALMODE                    (0x0UL<<1)
#define DEV_PWM_CTL_DutyMode_MODE_BREATHMODE                    (0x1UL<<1)
#define DEV_PWM_CTL_DutyMode_MODE_SOFTMODE                      (0x2UL<<1)
#define DEV_PWM_CTL_DutyMode_MODE_PDMMODE                       (0x3UL<<1)
#define DEV_PWM_CTL_DutyMode_MODE_MASK                          (0x3UL<<1)
#define DEV_PWM_CTL_DutyMode_EN                                 (0x1UL<<0)
/****PWMn_CTL end****/


/***********************************PWMn_CTL***********************************/
#define DEV_PWM_CTL_BreathMode_HNUM_MASK                        (0xffUL<<24)
#define DEV_PWM_CTL_BreathMode_LNUM_MASK                        (0xffUL<<16)
#define DEV_PWM_CTL_BreathMode_QNUM_MASK                        (0xfUL<<4)
#define DEV_PWM_CTL_BreathMode_MODE_NORMALMODE                  (0x0UL<<1)
#define DEV_PWM_CTL_BreathMode_MODE_BREATHMODE                  (0x1UL<<1)
#define DEV_PWM_CTL_BreathMode_MODE_SOFTMODE                    (0x2UL<<1)
#define DEV_PWM_CTL_BreathMode_MODE_PDMMODE                     (0x3UL<<1)
#define DEV_PWM_CTL_BreathMode_MODE_MASK                        (0x3UL<<1)
#define DEV_PWM_CTL_BreathMode_EN                               (0x1UL<<0)
/****PWMn_CTL end****/


/***********************************PWMn_CTL***********************************/
#define DEV_PWM_CTL_SoftMode_OUT_SET                            (0x1UL<<31)
#define DEV_PWM_CTL_SoftMode_OUT_VAL_MASK                       (0x3UL<<28)
#define DEV_PWM_CTL_SoftMode_MOD_OUT                            (0x1UL<<26)
#define DEV_PWM_CTL_SoftMode_CLK_OUT                            (0x1UL<<25)
#define DEV_PWM_CTL_SoftMode_SGN_FMT_SIGNEDMAGNITUDE            (0x0UL<<24)
#define DEV_PWM_CTL_SoftMode_SGN_FMT_SIGNEDCOMPLEMENT           (0x1UL<<24)
#define DEV_PWM_CTL_SoftMode_SGN_FMT_MASK                       (0x1UL<<24)
#define DEV_PWM_CTL_SoftMode_OUT_FMT_SINGLEEND                  (0x0UL<<22)
#define DEV_PWM_CTL_SoftMode_OUT_FMT_OVERTURN                   (0x1UL<<22)
#define DEV_PWM_CTL_SoftMode_OUT_FMT_DIFFERENCE                 (0x2UL<<22)
#define DEV_PWM_CTL_SoftMode_OUT_FMT_CLASS_D                    (0x3UL<<22)
#define DEV_PWM_CTL_SoftMode_OUT_FMT_MASK                       (0x3UL<<22)
#define DEV_PWM_CTL_SoftMode_FIFO_RST_FIFOWORK                  (0x0UL<<21)
#define DEV_PWM_CTL_SoftMode_FIFO_RST_FIFORESET                 (0x1UL<<21)
#define DEV_PWM_CTL_SoftMode_FIFO_RST_MASK                      (0x1UL<<21)
#define DEV_PWM_CTL_SoftMode_FIFO_THR_MASK                      (0x1fUL<<16)
#define DEV_PWM_CTL_SoftMode_LEN_256_512_1024_65536             (0x0UL<<15)
#define DEV_PWM_CTL_SoftMode_LEN_250_500_1000_64000             (0x1UL<<15)
#define DEV_PWM_CTL_SoftMode_LEN_MASK                           (0x1UL<<15)
#define DEV_PWM_CTL_SoftMode_FIFO_CONT_STOPWHENFIFOEMPTY        (0x0UL<<14)
#define DEV_PWM_CTL_SoftMode_FIFO_CONT_CONTINUEWHENFIFOEMPTY_OUTPUTLASTPWM_TX_DAT   (0x1UL<<14)
#define DEV_PWM_CTL_SoftMode_FIFO_CONT_MASK                     (0x1UL<<14)
#define DEV_PWM_CTL_SoftMode_FMT_1DATA                          (0x0UL<<12)
#define DEV_PWM_CTL_SoftMode_FMT_2DATA                          (0x1UL<<12)
#define DEV_PWM_CTL_SoftMode_FMT_3DATA                          (0x2UL<<12)
#define DEV_PWM_CTL_SoftMode_FMT_4DATA                          (0x3UL<<12)
#define DEV_PWM_CTL_SoftMode_FMT_MASK                           (0x3UL<<12)
#define DEV_PWM_CTL_SoftMode_RPT_MASK                           (0xfUL<<8)
#define DEV_PWM_CTL_SoftMode_WIDTH_MASK                         (0xfUL<<4)
#define DEV_PWM_CTL_SoftMode_MODE_NORMALMODE                    (0x0UL<<1)
#define DEV_PWM_CTL_SoftMode_MODE_BREATHMODE                    (0x1UL<<1)
#define DEV_PWM_CTL_SoftMode_MODE_SOFTMODE                      (0x2UL<<1)
#define DEV_PWM_CTL_SoftMode_MODE_PDMMODE                       (0x3UL<<1)
#define DEV_PWM_CTL_SoftMode_MODE_MASK                          (0x3UL<<1)
#define DEV_PWM_CTL_SoftMode_EN                                 (0x1UL<<0)
/****PWMn_CTL end****/


/***********************************PWMn_CTL***********************************/
#define DEV_PWM_CTL_PDMMode_CLK_OUT                             (0x1UL<<25)
#define DEV_PWM_CTL_PDMMode_FIFO_RST_FIFOWORK                   (0x0UL<<21)
#define DEV_PWM_CTL_PDMMode_FIFO_RST_FIFORESET                  (0x1UL<<21)
#define DEV_PWM_CTL_PDMMode_FIFO_RST_MASK                       (0x1UL<<21)
#define DEV_PWM_CTL_PDMMode_FIFO_THR_MASK                       (0x1fUL<<16)
#define DEV_PWM_CTL_PDMMode_FIFO_CONT_STOPWHENFIFOEMPTY         (0x0UL<<14)
#define DEV_PWM_CTL_PDMMode_FIFO_CONT_CONTINUEWHENFIFOEMPTY     (0x1UL<<14)
#define DEV_PWM_CTL_PDMMode_FIFO_CONT_MASK                      (0x1UL<<14)
#define DEV_PWM_CTL_PDMMode_MODE_NORMALMODE                     (0x0UL<<1)
#define DEV_PWM_CTL_PDMMode_MODE_BREATHMODE                     (0x1UL<<1)
#define DEV_PWM_CTL_PDMMode_MODE_SOFTMODE                       (0x2UL<<1)
#define DEV_PWM_CTL_PDMMode_MODE_PDMMODE                        (0x3UL<<1)
#define DEV_PWM_CTL_PDMMode_MODE_MASK                           (0x3UL<<1)
#define DEV_PWM_CTL_PDMMode_EN                                  (0x1UL<<0)
/****PWMn_CTL end****/


/***********************************PWM0_TX_DAT***********************************/
#define DEV_PWM_PWM0_TX_DAT_DATA_MASK                           (0xffffffffUL<<0)
/****PWM0_TX_DAT end****/


/***********************************PWM0_STA***********************************/
#define DEV_PWM_PWM0_STA_WLEVEL_MASK                            (0x1fUL<<2)
#define DEV_PWM_PWM0_STA_EMPTY                                  (0x1UL<<1)
#define DEV_PWM_PWM0_STA_FULL                                   (0x1UL<<0)
/****PWM0_STA end****/


/***********************************PWM2_TX_DAT***********************************/
#define DEV_PWM_PWM2_TX_DAT_DATA_MASK                           (0xffffffffUL<<0)
/****PWM2_TX_DAT end****/


/***********************************PWM2_STA***********************************/
#define DEV_PWM_PWM2_STA_WLEVEL_MASK                            (0x1fUL<<2)
#define DEV_PWM_PWM2_STA_EMPTY                                  (0x1UL<<1)
#define DEV_PWM_PWM2_STA_FULL                                   (0x1UL<<0)
/****PWM2_STA end****/


/***********************************PWM_PD***********************************/
#define DEV_PWM_PD_DAT2_END                                     (0x1UL<<24)
#define DEV_PWM_PD_DAT0_END                                     (0x1UL<<23)
#define DEV_PWM_PD_FIFO1_UF                                     (0x1UL<<22)
#define DEV_PWM_PD_FIFO1_OF                                     (0x1UL<<21)
#define DEV_PWM_PD_FIFO1_THR                                    (0x1UL<<20)
#define DEV_PWM_PD_FIFO0_UF                                     (0x1UL<<18)
#define DEV_PWM_PD_FIFO0_OF                                     (0x1UL<<17)
#define DEV_PWM_PD_FIFO0_THR                                    (0x1UL<<16)
#define DEV_PWM_PD_BTH_END_MASK                                 (0xffUL<<8)
#define DEV_PWM_PD_PWM_END_MASK                                 (0xffUL<<0)
/****PWM_PD end****/


/***********************************PWM_IE***********************************/
#define DEV_PWM_IE_DMA1_EN                                      (0x1UL<<29)
#define DEV_PWM_IE_DMA0_EN                                      (0x1UL<<28)
#define DEV_PWM_IE_DAT2_END                                     (0x1UL<<24)
#define DEV_PWM_IE_DAT0_END                                     (0x1UL<<23)
#define DEV_PWM_IE_FIFO1_UF                                     (0x1UL<<22)
#define DEV_PWM_IE_FIFO1_OF                                     (0x1UL<<21)
#define DEV_PWM_IE_FIFO1_THR                                    (0x1UL<<20)
#define DEV_PWM_IE_FIFO0_UF                                     (0x1UL<<18)
#define DEV_PWM_IE_FIFO0_OF                                     (0x1UL<<17)
#define DEV_PWM_IE_FIFO0_THR                                    (0x1UL<<16)
#define DEV_PWM_IE_BTH_END_MASK                                 (0xffUL<<8)
#define DEV_PWM_IE_PWM_END_MASK                                 (0xffUL<<0)
/****PWM_IE end****/


/***********************************PWM_PHA0***********************************/
#define DEV_PWM_PHA0_DUTY2_MASK                                 (0x1ffUL<<18)
#define DEV_PWM_PHA0_DUTY1_MASK                                 (0x1ffUL<<9)
#define DEV_PWM_PHA0_DUTY0_MASK                                 (0x1ffUL<<0)
/****PWM_PHA0 end****/


/***********************************PWM_PHA1***********************************/
#define DEV_PWM_PHA1_LEN(total_cycle)                           (((total_cycle)-1)<<0)
#define DEV_PWM_PHA1_LEN_MASK                                   (0xffUL<<0)
/****PWM_PHA1 end****/


/***********************************PWM_DTR***********************************/
#define DEV_PWM_DTR_CNT_MODE_CNT_MODE_UP                        (0x0UL<<26)
#define DEV_PWM_DTR_CNT_MODE_CNT_MODE_DOWN                      (0x1UL<<26)
#define DEV_PWM_DTR_CNT_MODE_CNT_MODE_CENTER                    (0x2UL<<26)
#define DEV_PWM_DTR_CNT_MODE_MASK                               (0x3UL<<26)
#define DEV_PWM_DTR_OC2L_IP                                     (0x1UL<<25)
#define DEV_PWM_DTR_OC2H_IP                                     (0x1UL<<24)
#define DEV_PWM_DTR_OC2L_P                                      (0x1UL<<23)
#define DEV_PWM_DTR_OC2H_P                                      (0x1UL<<22)
#define DEV_PWM_DTR_OC1L_IP                                     (0x1UL<<21)
#define DEV_PWM_DTR_OC1H_IP                                     (0x1UL<<20)
#define DEV_PWM_DTR_OC1L_P                                      (0x1UL<<19)
#define DEV_PWM_DTR_OC1H_P                                      (0x1UL<<18)
#define DEV_PWM_DTR_OC0L_IP                                     (0x1UL<<17)
#define DEV_PWM_DTR_OC0H_IP                                     (0x1UL<<16)
#define DEV_PWM_DTR_OC0L_P                                      (0x1UL<<15)
#define DEV_PWM_DTR_OC0H_P                                      (0x1UL<<14)
#define DEV_PWM_DTR_DEADTIME(deadtime,pwm_clk)                  (((deadtime)*(1/(pwm_clk)))<<6)
#define DEV_PWM_DTR_DEADTIME_MASK                               (0xffUL<<6)
#define DEV_PWM_DTR_OC2_ENABLE                                  (0x1UL<<5)
#define DEV_PWM_DTR_OC1_ENABLE                                  (0x1UL<<4)
#define DEV_PWM_DTR_OC0_ENABLE                                  (0x1UL<<3)
#define DEV_PWM_DTR_PWM2_EN                                     (0x1UL<<2)
#define DEV_PWM_DTR_PWM1_EN                                     (0x1UL<<1)
#define DEV_PWM_DTR_PWM0_EN                                     (0x1UL<<0)
/****PWM_DTR end****/


/***********************************DEV_PWM register***********************************/
typedef struct
{

    __IO    uint32_t    CTL[8];                                  /* 0x0    PWM0 Control */
    __O     uint32_t    PWM0_TX_DAT;                             /* 0x20    FIFO Write Data */
    __I     uint32_t    PWM0_STA;                                /* 0x24    FIFO Status */
    __O     uint32_t    PWM2_TX_DAT;                             /* 0x28    FIFO Write Data */
    __I     uint32_t    PWM2_STA;                                /* 0x2c    FIFO Status */
    uint32_t    RESERVED0[4];
    __IO    uint32_t    PD;                                      /* 0x40    PWM Pending */
    __IO    uint32_t    IE;                                      /* 0x44    PWM Interrupt Enable */
    uint32_t    RESERVED1[3];
    __IO    uint32_t    PHA0;                                    /* 0x54    DEADTIME Control PWM_Duty */
    __IO    uint32_t    PHA1;                                    /* 0x58    DEADTIME Control PWM_Len */
    __IO    uint32_t    DTR;                                     /* 0x5c    DEADTIME Control Configuration */
} DEV_PWM_RegDef;
/****DEV_PWM end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
