/*
* Copyright (c) 2023-2028, SpaceTouch Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date          Author      Notes
* 2023-07-18    zhixiongl       the first version
*/

#ifndef SPV_HAL_USBD_REG_H
#define SPV_HAL_USBD_REG_H

#ifdef __cplusplus
extern "C"
{
#endif

#include "platform.h"

/*-----------COMMON REGISTERS----------------*/
#define REG_FADDR                       _IO_((uint32_t)0x200d0000)//*(volatile uint32_t *)(0x200d0000)
#define REG_POWER                       _IO_((uint32_t)0x200d0000) //0x200d0001
#define REG_POWER_ISO_UPDATE            (0x01 << 7)
#define REG_POWER_SOFT_CONN             (0x01 << 6)
#define REG_POWER_HS_ENAB               (0x01 << 5)
#define REG_POWER_HS_MODE               (0x01 << 4)
#define REG_POWER_RESET                 (0x01 << 3)
#define REG_POWER_RESUME                (0x01 << 2)
#define REG_POWER_SUSPEND_MODE          (0x01 << 1)
#define REG_POWER_ENABLE_SUSPENDM       (0x01 << 0)

#define REG_INTRTX                      _IO_((uint32_t)0x200d0000)//0x200d0002
#define REG_INTRTX_EP(N)                (0x01 << N)
#define REG_INTRTXE                     _IO_((uint32_t)0x200d0004)//0x200d0006
#define REG_INTRTXE_EP(N)               (0x01 << N)

#define REG_INTRRX                      _IO_((uint32_t)0x200d0004)
#define REG_INTRRX_EP(N)                (0x01 << N)
#define REG_INTRRXE                     _IO_((uint32_t)0x200d0008)//*(volatile uint16_t *)(0x200d0000 + 0x08)
#define REG_INTRRXE_EP(N)               (0x01 << N)

#define REG_INTRUSB                     _IO_((uint32_t)0x200d0008)//0x200d000A
#define REG_INTRUSB_VBUS_ERROR          (0X01 << 7)
#define REG_INTRUSB_SESS_REQ            (0X01 << 6)
#define REG_INTRUSB_DISCON              (0X01 << 5)
#define REG_INTRUSB_CONN                (0X01 << 4)
#define REG_INTRUSB_SOF                 (0X01 << 3)
#define REG_INTRUSB_RESET               (0x01 << 2)
#define REG_INTRUSB_RESUME              (0X01 << 1)
#define REG_INTRUSB_SUSPEND             (0X01 << 0)

#define REG_INTRUSBE                    _IO_((uint32_t)0x200d0008)//0x200d000B
#define REG_INTRUSBE_VBUS_ERROR         (0x01 << 7)
#define REG_INTRUSBE_SESS_REQ           (0x01 << 6)
#define REG_INTRUSBE_DISCON             (0x01 << 5)
#define REG_INTRUSBE_CONN               (0x01 << 4)
#define REG_INTRUSBE_SOF                (0x01 << 3)
#define REG_INTRUSBE_RESET              (0x01 << 2)
#define REG_INTRUSBE_RESUME             (0x01 << 1)
#define REG_INTRUSBE_SUSPEND            (0x01 << 0)

#define REG_FRAME                       _IO_((uint32_t)0x200d000C)//*(volatile uint16_t *)(0x200d0000 + 0x0c)
#define REG_INDEX                       _IO_((uint32_t)0x200d000C)//0x200d000E
#define REG_TESTMODE                    _IO_((uint32_t)0x200d000C)//0x200d000F

#define REG_DEVCTL                      _IO_((uint32_t)0x200d0060)
#define REG_DEVCTL_SESSION              (0x01 << 0)

/*-----------INDEXED REGISTERS----------------*/
#define REG_CSR0                        _IO_((uint32_t)0x200d0010)//0x200d0012
#define REG_CSR0_FLUSHFIFO              (0x01 << 8)
#define REG_CSR0_SERVICED_SETUPEND      (0x01 << 7)
#define REG_CSR0_SERVICED_RXPKTRDY      (0x01 << 6)
#define REG_CSR0_SENDSTALL              (0x01 << 5)
#define REG_CSR0_SETUPEND               (0x01 << 4)
#define REG_CSR0_DATAEND                (0x01 << 3)
#define REG_CSR0_SENTSTALL              (0x01 << 2)
#define REG_CSR0_TXPKTRDY               (0x01 << 1)
#define REG_CSR0_RXPKTRDY               (0x01 << 0)

#define REG_TXCSR                       _IO_((uint32_t)0x200d0010)//0x200d0012
#define REG_TXCSR_AUTOSET               (0x01 << 15)
#define REG_TXCSR_SERVICED_ISO          (0x01 << 14)
#define REG_TXCSR_SERVICED_MODE         (0x01 << 13)
#define REG_TXCSR_DMAREQ_ENAB           (0x01 << 12)
#define REG_TXCSR_FRCDATATOG            (0x01 << 11)
#define REG_TXCSR_DMAREQ_MODE           (0x01 << 10)

#define REG_TXCSR_INCOMPTX              (0x01 << 7)
#define REG_TXCSR_CLRDATATOG            (0x01 << 6)
#define REG_TXCSR_SENTSTALL             (0x01 << 5)
#define REG_TXCSR_SENDSTALL             (0x01 << 4)
#define REG_TXCSR_FLUSHFIFO             (0x01 << 3)
#define REG_TXCSR_UNDERRUN              (0x01 << 2)
#define REG_TXCSR_FIFO_NOTEMPTY         (0x01 << 1)
#define REG_TXCSR_TXPKTRDY              (0x01 << 0)

#define REG_RXCSR                       _IO_((uint32_t)0x200d0014)//0x200d0016
#define REG_RXCSR_AUTOCLEAR             (0x01 << 15)
#define REG_RXCSR_ISO                   (0x01 << 14)
#define REG_RXCSR_DMAREQ_ENAB           (0x01 << 13)
#define REG_RXCSR_DISNYET               (0x01 << 12)
#define REG_RXCSR_DMAREQ_MODE           (0x01 << 11)
#define REG_RXCSR_INCOMPRX              (0x01 << 8)

#define REG_RXCSR_CLRDATATOG            (0x01 << 7)
#define REG_RXCSR_SENTSTALL             (0x01 << 6)
#define REG_RXCSR_SENDSTALL             (0x01 << 5)
#define REG_RXCSR_FLUSHFIFO             (0x01 << 4)
#define REG_RXCSR_DATAERROR             (0x01 << 3)
#define REG_RXCSR_OVERRUN               (0x01 << 2)
#define REG_RXCSR_FIFOFULL              (0x01 << 1)
#define REG_RXCSR_RXPKTRDY              (0x01 << 0)

#define REG_COUNT0                      _IO_((uint32_t)0x200d0018)
#define REG_RXCOUNT                     _IO_((uint32_t)0x200d0018)
#define REG_CONFIGDATA                  _IO_((uint32_t)0x200d001C)//0x200d001F  
#define REG_CONFIGDATA_MPREXE           (0x01 << 7)
#define REG_CONFIGDATA_MPTXE            (0x01 << 6)
#define REG_CONFIGDATA_BIGENDIAN        (0x01 << 5)
#define REG_CONFIGDATA_HBRXE            (0x01 << 4)
#define REG_CONFIGDATA_HBTXE            (0x01 << 3)
#define REG_CONFIGDATA_DYNFIFO_SIZING   (0x01 << 2)
#define REG_CONFIGDATA_SOFTCONE         (0x01 << 1)
#define REG_CONFIGDATA_UTMIDATAWIDTH    (0x01 << 0)

#define REG_FIFOSIZE                    _IO_((uint32_t)0x200d001C)//0x200d001F
#define REG_TXMAXP                      _IO_((uint32_t)0x200d0010)
#define REG_RXMAXP                      _IO_((uint32_t)0x200d0014)

/*-----------ADDITIONAL CONTROL / STATUS REGISTERS----------------*/
//VControl/VStatus ??
//HWVers   ??

/*-----------ADDITIONAL CONFIGURATION REGISTERS----------------*/
//EPInfo ??
//RAMInfo??
//LinkInfo??
//HS_EOF1??
//FS_EOF1??

/*-----------FIFOx----------------*/
#define REG_FIFO_EP0         _IO_((uint32_t)0x200d0020)

/*-----------DYNAMIC FIFO SIZING----------------*/
#define REG_TXFIFOSZ        _IO_((uint32_t)0x200d0060)//0x200d0062
#define REG_RXFIFOSZ        _IO_((uint32_t)0x200d0060)//0x200d0063
#define REG_TXFIFOADD       _IO_((uint32_t)0x200d0064)
#define REG_RXFIFOADD       _IO_((uint32_t)0x200d0064)//0x200d0066

/*-----------DMA REGISTERS----------------*/
#define REG_DMA_INTRDMA     _IO_((uint32_t)0x200d0200)
#define REG_DMA_CNTL(N)     _IO_((uint32_t)0x200d0204 + ((N)<<4)) //N对应端点？端点0没有DMA？
#define REG_DMA_ADDR(N)     _IO_((uint32_t)0x200d0208 + ((N)<<4))
#define REG_DMA_COUNT(N)    _IO_((uint32_t)0x200d020C + ((N)<<4))

/*-----------UREG----------------*/
#define USB_PHY_CTRL0       _IO_((uint32_t)0x20006000)
#define USB_PLL_CTRL        _IO_((uint32_t)0x2000600C)
// ......


/* Define standard constants */
// #define TRUE   1
// #define FALSE  0
// #ifndef NULL
// #define NULL 0
//#endif


void usb_write_reg(uint32_t data, uint32_t *baseAddr, uint8_t offset, uint8_t dataWidth);
uint32_t usb_read_reg(uint32_t *baseAddr, uint8_t offset, uint8_t dataWidth);


void usb_write_faddr(uint8_t addr);
uint8_t usb_read_faddr(void);
void usb_write_power(uint8_t command);
uint8_t usb_read_power(void);
uint16_t usb_read_intrtx(void);
uint16_t usb_read_intrrx(void);
void usb_write_intrtxe(uint16_t intrtxe);
uint16_t usb_read_intrtxe(void);
void usb_write_intrrxe(uint16_t intrrxe);
uint16_t usb_read_intrrxe(void);
uint8_t usb_read_intrusb(void);
void usb_write_intrusbe(uint16_t intrusbe);
uint8_t usb_read_intrusbe(void);
uint16_t usb_read_frame(void);
void usb_write_index(uint8_t index);
uint8_t usb_read_index(void);
void usb_write_testmode(uint8_t reg);
uint8_t usb_read_testmode(void);
uint8_t usb_read_devctl(void);


void usb_write_csr0(uint16_t csr);
uint8_t usb_read_csr0(void);
void usb_write_txcsr(uint16_t txcsr);
uint16_t usb_read_txcsr(void);
void usb_write_rxcsr(uint16_t rxcsr);
uint16_t usb_read_rxcsr(void);
uint8_t usb_read_count0(void);
uint16_t usb_read_rxcount(void);
uint8_t usb_read_configdata(void);
uint8_t usb_read_fifosize(void);
void usb_write_txmax(uint16_t txmax);
uint16_t usb_read_txmax(void);
void usb_write_rxmax(uint16_t rxmax);
uint16_t usb_read_rxmax(void);


void usb_write_tx_fifosize(uint8_t txfifosz);
uint8_t usb_read_tx_fifosize(void);
void usb_write_rx_fifosize(uint16_t rxfifosz);
uint8_t usb_read_rx_fifosize(void);
void usb_write_tx_fifoadd(uint16_t txfifoadd);
uint16_t usb_read_tx_fifoadd(void);
void usb_write_rx_fifoadd(uint16_t rxfifoadd);
uint16_t usb_read_rx_fifoadd(void);


void write_dma_cntl(int endp, uint16_t param);
uint16_t read_dma_cntl(int endp);
void write_dma_addr(int endp, uint32_t param);
uint16_t read_dma_addr(int endp);
void write_dma_count(int endp, uint32_t param);
uint16_t read_dma_count(int endp);


/* lzx&D 没有读写函数的寄存器：
VControl/VStatus ??
HWVers   ??

EPInfo ??
RAMInfo??
LinkInfo??
HS_EOF1??
FS_EOF1??

FIFOx

INTRDMA
*/

#ifdef __cplusplus
}
#endif

#endif

