#ifndef __DEV_GPIO_H__
#define __DEV_GPIO_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************GPIOn_CTL***********************************/
#define DEV_GPIO_CTL_IV_DISABLE                                 (0x0UL<<14)
#define DEV_GPIO_CTL_IV_ENABLE                                  (0x1UL<<14)
#define DEV_GPIO_CTL_IV_MASK                                    (0x1UL<<14)
#define DEV_GPIO_CTL_OV_DISABLE                                 (0x0UL<<13)
#define DEV_GPIO_CTL_OV_ENABLE                                  (0x1UL<<13)
#define DEV_GPIO_CTL_OV_MASK                                    (0x1UL<<13)
#define DEV_GPIO_CTL_DS                                         (0x1UL<<12)
#define DEV_GPIO_CTL_FAST_DISABLE                               (0x0UL<<11)
#define DEV_GPIO_CTL_FAST_ENABLE                                (0x1UL<<11)
#define DEV_GPIO_CTL_FAST_MASK                                  (0x1UL<<11)
#define DEV_GPIO_CTL_LB_DISABLE                                 (0x0UL<<10)
#define DEV_GPIO_CTL_LB_ENABLE                                  (0x1UL<<10)
#define DEV_GPIO_CTL_LB_MASK                                    (0x1UL<<10)

#define DEV_GPIO_CTL_O                                          (0x1UL<<9)
#define DEV_GPIO_CTL_PS_PULLDOWN                                (0x0UL<<7)
#define DEV_GPIO_CTL_PS_PULLUP                                  (0x1UL<<7)
#define DEV_GPIO_CTL_PS_MASK                                    (0x1UL<<7)
#define DEV_GPIO_CTL_PE_DISABLE                                 (0x0UL<<6)
#define DEV_GPIO_CTL_PE_ENABLE                                  (0x1UL<<6)
#define DEV_GPIO_CTL_PE_MASK                                    (0x1UL<<6)
#define DEV_GPIO_CTL_IE_DISABLE                                 (0x0UL<<5)
#define DEV_GPIO_CTL_IE_ENABLE                                  (0x1UL<<5)
#define DEV_GPIO_CTL_IE_MASK                                    (0x1UL<<5)
#define DEV_GPIO_CTL_OE_DISABLE                                 (0x0UL<<4)
#define DEV_GPIO_CTL_OE_ENABLE                                  (0x1UL<<4)
#define DEV_GPIO_CTL_OE_MASK                                    (0x1UL<<4)
#define DEV_GPIO_CTL_MFP_MASK                                   (0xfUL<<0)
/****GPIOn_CTL end****/


/***********************************GPIO_OUT0***********************************/
#define DEV_GPIO_OUT0_MASK                                      (0xffffffffUL<<0)
/****GPIO_OUT0 end****/


/***********************************GPIO_OUT1***********************************/
#define DEV_GPIO_OUT1_MASK                                      (0xffUL<<0)
/****GPIO_OUT1 end****/


/***********************************GPIO_IN0***********************************/
#define DEV_GPIO_IN0_MASK                                       (0xffffffffUL<<0)
/****GPIO_IN0 end****/


/***********************************GPIO_IN1***********************************/
#define DEV_GPIO_IN1_MASK                                       (0xffUL<<0)
/****GPIO_IN1 end****/


/***********************************GPIO_RSTN***********************************/
#define DEV_GPIO_RSTN_PU_DISABLE                                (0x0UL<<9)
#define DEV_GPIO_RSTN_PU_ENABLE                                 (0x1UL<<9)
#define DEV_GPIO_RSTN_PU_MASK                                   (0x1UL<<9)
#define DEV_GPIO_RSTN_EN_DISABLE                                (0x0UL<<8)
#define DEV_GPIO_RSTN_EN_ENABLE                                 (0x1UL<<8)
#define DEV_GPIO_RSTN_EN_MASK                                   (0x1UL<<8)
#define DEV_GPIO_RSTN_SEL_GPIO                                  (0x27UL<<0)
#define DEV_GPIO_RSTN_SEL_MASK                                  (0x3fUL<<0)
/****GPIO_RSTN end****/


/***********************************GPIO_ECLK***********************************/
#define DEV_GPIO_ECLK_EN_DISABLE                                (0x0UL<<8)
#define DEV_GPIO_ECLK_EN_ENABLE                                 (0x1UL<<8)
#define DEV_GPIO_ECLK_EN_MASK                                   (0x1UL<<8)
#define DEV_GPIO_ECLK_SEL_GPIO                                  (0x1fUL<<0)
#define DEV_GPIO_ECLK_SEL_MASK                                  (0x3fUL<<0)
/****GPIO_ECLK end****/


/***********************************GPIO_ECLK2***********************************/
#define DEV_GPIO_ECLK2_EN_DISABLE                               (0x0UL<<8)
#define DEV_GPIO_ECLK2_EN_ENABLE                                (0x1UL<<8)
#define DEV_GPIO_ECLK2_EN_MASK                                  (0x1UL<<8)
#define DEV_GPIO_ECLK2_SEL_GPIO                                 (0x1fUL<<0)
#define DEV_GPIO_ECLK2_SEL_MASK                                 (0x3fUL<<0)
/****GPIO_ECLK2 end****/


/***********************************GPIO_ICn***********************************/
#define DEV_GPIO_ICn_EVENT_NONE                                 (0x0UL<<6)
#define DEV_GPIO_ICn_EVENT_RISE                                 (0x1UL<<6)
#define DEV_GPIO_ICn_EVENT_FALL                                 (0x2UL<<6)
#define DEV_GPIO_ICn_EVENT_BOTHEDGE                             (0x3UL<<6)
#define DEV_GPIO_ICn_EVENT_HIGH                                 (0x4UL<<6)
#define DEV_GPIO_ICn_EVENT_LOW                                  (0x5UL<<6)
#define DEV_GPIO_ICn_EVENT_MASK                                 (0x7UL<<6)
#define DEV_GPIO_ICn_SOURCE_MASK                                (0x3fUL<<0)
/****GPIO_ICn end****/


/***********************************GPIO_IE0***********************************/
#define DEV_GPIO_IE0_MASK                                       (0xfUL<<0)
/****GPIO_IE0 end****/


/***********************************GPIO_IE1***********************************/
#define DEV_GPIO_IE1_MASK                                       (0xfUL<<0)
/****GPIO_IE1 end****/


/***********************************GPIO_PD***********************************/
#define DEV_GPIO_PD_MASK                                        (0xfUL<<0)
/****GPIO_PD end****/


/***********************************DBIO_CTL***********************************/
#define DEV_GPIO_DBIO_CTL_BIT_SEL_MASK                          (0xfUL<<8)
#define DEV_GPIO_DBIO_CTL_BIT_EN                                (0x1UL<<7)
#define DEV_GPIO_DBIO_CTL_GRP_SEL_MASK                          (0x3fUL<<0)
/****DBIO_CTL end****/


/***********************************DBIO_OE0***********************************/
#define DEV_GPIO_DBIO_OE0_MASK                                  (0xffffffffUL<<0)
/****DBIO_OE0 end****/


/***********************************DBIO_IE0***********************************/
#define DEV_GPIO_DBIO_IE0_MASK                                  (0xffffffffUL<<0)
/****DBIO_IE0 end****/


/***********************************DBIO_IE1***********************************/
#define DEV_GPIO_DBIO_IE1_MASK                                  (0xffUL<<0)
/****DBIO_IE1 end****/


/***********************************DBIO_OUT0***********************************/
#define DEV_GPIO_DBIO_OUT0_MASK                                 (0xffffffffUL<<0)
/****DBIO_OUT0 end****/


/***********************************DBIO_OUT1***********************************/
#define DEV_GPIO_DBIO_OUT1_MASK                                 (0xffUL<<0)
/****DBIO_OUT1 end****/


/***********************************DEV_GPIO register***********************************/
typedef struct
{
    __IO    uint32_t    CTL[40];                                 /* 0x0    GPIO Control */
    uint32_t    RESERVED0[24];
    __IO    uint32_t    OUT0;                                    /* 0x100    GPIO Output0 */
    __IO    uint32_t    OUT1;                                    /* 0x104    GPIO Output1 */
    uint32_t    RESERVED1[2];
    __I     uint32_t    IN0;                                     /* 0x110    GPIO Input0 */
    __I     uint32_t    IN1;                                     /* 0x114    GPIO Input1 */
    uint32_t    RESERVED2[2];
    __IO    uint32_t    RSTN;                                    /* 0x120    GPIO Reset */
    uint32_t    RESERVED3;
    __IO    uint32_t    ECLK;                                    /* 0x128    GPIO External Clock */
    __IO    uint32_t    ECLK2;                                   /* 0x12c    GPIO External Clock2 */
    uint32_t    RESERVED4[52];
    __IO    uint32_t    ICn[4];                                  /* 0x200    GPIO Interrupt Control */
    uint32_t    RESERVED5[4];
    __IO    uint32_t    IE0;                                     /* 0x220    GPIO Interrupt Enable */
    __IO    uint32_t    IE1;                                     /* 0x224    GPIO Interrupt Enable */
    __IO    uint32_t    PD;                                      /* 0x228    GPIO Pending */
    uint32_t    RESERVED6[53];
    __IO    uint32_t    DBIO_CTL;                                /* 0x300    Debug IO Control */
    uint32_t    RESERVED7[3];
    __IO    uint32_t    DBIO_OE0;                                /* 0x310    Debug IO Output Enable */
    uint32_t    RESERVED8[3];
    __IO    uint32_t    DBIO_IE0;                                /* 0x320    Debug IO Input Enable */
    __IO    uint32_t    DBIO_IE1;                                /* 0x324    Debug IO Input Enable */
    uint32_t    RESERVED9[2];
    __I     uint32_t    DBIO_OUT0;                               /* 0x330    Debug IO Ouput Value for Read back */
    __I     uint32_t    DBIO_OUT1;                               /* 0x334    Debug IO Ouput Value for Read back */
} DEV_GPIO_RegDef;
/****DEV_GPIO end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/


#define DEV_GPIO_CTRL_MFP_FUN_0         0x0UL
#define DEV_GPIO_CTRL_MFP_FUN_1         0x1UL
#define DEV_GPIO_CTRL_MFP_FUN_2         0x2UL
#define DEV_GPIO_CTRL_MFP_FUN_3         0x3UL
#define DEV_GPIO_CTRL_MFP_FUN_4         0x4UL
#define DEV_GPIO_CTRL_MFP_FUN_5         0x5UL
#define DEV_GPIO_CTRL_MFP_FUN_6         0x6UL
#define DEV_GPIO_CTRL_MFP_FUN_7         0x7UL
#define DEV_GPIO_CTRL_MFP_FUN_8         0x8UL
#define DEV_GPIO_CTRL_MFP_FUN_9         0x9UL
#define DEV_GPIO_CTRL_MFP_FUN_10        0xaUL
#define DEV_GPIO_CTRL_MFP_FUN_11        0xbUL
#define DEV_GPIO_CTRL_MFP_FUN_12        0xcUL
#define DEV_GPIO_CTRL_MFP_FUN_13        0xdUL
#define DEV_GPIO_CTRL_MFP_FUN_14        0xeUL
#define DEV_GPIO_CTRL_MFP_FUN_15        0xfUL


#endif
