#ifndef __DEV_DAC_FIELD_H__
#define __DEV_DAC_FIELD_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************HNL_IIRn_B0***********************************/
typedef struct
{
    __IO uint32_t B0                  : 32;
} DEV_DAC_HNL_IIRn_B0_Field;
/****DEV_DACHNL_IIRn_B0 end****/

/***********************************HNL_IIRn_B1***********************************/
typedef struct
{
    __IO uint32_t B1                  : 32;
} DEV_DAC_HNL_IIRn_B1_Field;
/****DEV_DACHNL_IIRn_B1 end****/

/***********************************HNL_IIRn_B2***********************************/
typedef struct
{
    __IO uint32_t B2                  : 32;
} DEV_DAC_HNL_IIRn_B2_Field;
/****DEV_DACHNL_IIRn_B2 end****/

/***********************************HNL_IIRn_A1***********************************/
typedef struct
{
    __IO uint32_t A1                  : 32;
} DEV_DAC_HNL_IIRn_A1_Field;
/****DEV_DACHNL_IIRn_A1 end****/

/***********************************HNL_IIRn_A2***********************************/
typedef struct
{
    __IO uint32_t A2                  : 32;
} DEV_DAC_HNL_IIRn_A2_Field;
/****DEV_DACHNL_IIRn_A2 end****/

/***********************************HNL_IIR7_B0***********************************/
typedef struct
{
    __IO uint32_t B0                  : 32;
} DEV_DAC_HNL_IIR7_B0_Field;
/****DEV_DACHNL_IIR7_B0 end****/

/***********************************HNL_IIR7_B1***********************************/
typedef struct
{
    __IO uint32_t B1                  : 32;
} DEV_DAC_HNL_IIR7_B1_Field;
/****DEV_DACHNL_IIR7_B1 end****/

/***********************************HNL_IIR7_B2***********************************/
typedef struct
{
    __IO uint32_t B2                  : 32;
} DEV_DAC_HNL_IIR7_B2_Field;
/****DEV_DACHNL_IIR7_B2 end****/

/***********************************HNL_IIR7_A1***********************************/
typedef struct
{
    __IO uint32_t A1                  : 32;
} DEV_DAC_HNL_IIR7_A1_Field;
/****DEV_DACHNL_IIR7_A1 end****/

/***********************************HNL_IIR7_A2***********************************/
typedef struct
{
    __IO uint32_t A2                  : 32;
} DEV_DAC_HNL_IIR7_A2_Field;
/****DEV_DACHNL_IIR7_A2 end****/

/***********************************HNR_IIRn_B0***********************************/
typedef struct
{
    __IO uint32_t B0                  : 32;
} DEV_DAC_HNR_IIRn_B0_Field;
/****DEV_DACHNR_IIRn_B0 end****/

/***********************************HNR_IIRn_B1***********************************/
typedef struct
{
    __IO uint32_t B1                  : 32;
} DEV_DAC_HNR_IIRn_B1_Field;
/****DEV_DACHNR_IIRn_B1 end****/

/***********************************HNR_IIRn_B2***********************************/
typedef struct
{
    __IO uint32_t B2                  : 32;
} DEV_DAC_HNR_IIRn_B2_Field;
/****DEV_DACHNR_IIRn_B2 end****/

/***********************************HNR_IIRn_A1***********************************/
typedef struct
{
    __IO uint32_t A1                  : 32;
} DEV_DAC_HNR_IIRn_A1_Field;
/****DEV_DACHNR_IIRn_A1 end****/

/***********************************HNR_IIRn_A2***********************************/
typedef struct
{
    __IO uint32_t A2                  : 32;
} DEV_DAC_HNR_IIRn_A2_Field;
/****DEV_DACHNR_IIRn_A2 end****/

/***********************************HNR_IIR7_B0***********************************/
typedef struct
{
    __IO uint32_t B0                  : 32;
} DEV_DAC_HNR_IIR7_B0_Field;
/****DEV_DACHNR_IIR7_B0 end****/

/***********************************HNR_IIR7_B1***********************************/
typedef struct
{
    __IO uint32_t B1                  : 32;
} DEV_DAC_HNR_IIR7_B1_Field;
/****DEV_DACHNR_IIR7_B1 end****/

/***********************************HNR_IIR7_B2***********************************/
typedef struct
{
    __IO uint32_t B2                  : 32;
} DEV_DAC_HNR_IIR7_B2_Field;
/****DEV_DACHNR_IIR7_B2 end****/

/***********************************HNR_IIR7_A1***********************************/
typedef struct
{
    __IO uint32_t A1                  : 32;
} DEV_DAC_HNR_IIR7_A1_Field;
/****DEV_DACHNR_IIR7_A1 end****/

/***********************************HNR_IIR7_A2***********************************/
typedef struct
{
    __IO uint32_t A2                  : 32;
} DEV_DAC_HNR_IIR7_A2_Field;
/****DEV_DACHNR_IIR7_A2 end****/

/***********************************RC_LMTH***********************************/
typedef struct
{
    __IO uint32_t LMTH                : 32;
} DEV_DAC_RC_LMTH_Field;
/****DEV_DACRC_LMTH end****/

/***********************************RC_SLOP***********************************/
typedef struct
{
    __IO uint32_t SLOP                : 32;
} DEV_DAC_RC_SLOP_Field;
/****DEV_DACRC_SLOP end****/

/***********************************RC_PEAK_AT***********************************/
typedef struct
{
    __IO uint32_t ATTACK_TIME         : 32;
} DEV_DAC_RC_PEAK_AT_Field;
/****DEV_DACRC_PEAK_AT end****/

/***********************************RC_PEAK_RT***********************************/
typedef struct
{
    __IO uint32_t RELEASE_TIME        : 32;
} DEV_DAC_RC_PEAK_RT_Field;
/****DEV_DACRC_PEAK_RT end****/

/***********************************RC_GAIN_AT***********************************/
typedef struct
{
    __IO uint32_t ATTACK_TIME         : 32;
} DEV_DAC_RC_GAIN_AT_Field;
/****DEV_DACRC_GAIN_AT end****/

/***********************************RC_GAIN_RT***********************************/
typedef struct
{
    __IO uint32_t RELEASE_TIME        : 32;
} DEV_DAC_RC_GAIN_RT_Field;
/****DEV_DACRC_GAIN_RT end****/

/***********************************SD_COE_B1***********************************/
typedef struct
{
    __IO uint32_t B1                  : 32;
} DEV_DAC_SD_COE_B1_Field;
/****DEV_DACSD_COE_B1 end****/

/***********************************SD_COE_B2***********************************/
typedef struct
{
    __IO uint32_t B2                  : 32;
} DEV_DAC_SD_COE_B2_Field;
/****DEV_DACSD_COE_B2 end****/

/***********************************SD_COE_A1***********************************/
typedef struct
{
    __IO uint32_t A1                  : 32;
} DEV_DAC_SD_COE_A1_Field;
/****DEV_DACSD_COE_A1 end****/

/***********************************SD_COE_A2***********************************/
typedef struct
{
    __IO uint32_t A2                  : 32;
} DEV_DAC_SD_COE_A2_Field;
/****DEV_DACSD_COE_A2 end****/

/***********************************SD_COE_A3***********************************/
typedef struct
{
    __IO uint32_t A3                  : 32;
} DEV_DAC_SD_COE_A3_Field;
/****DEV_DACSD_COE_A3 end****/

/***********************************CFG0***********************************/
typedef struct
{
    __IO uint32_t SIN_SRC             : 1;
    __IO uint32_t DMIC_SRC            : 1;
    __IO uint32_t IIR_SR_IN           : 2;
    __IO uint32_t SRC_SEL             : 1;
    __IO uint32_t DITHER_EN           : 1;
    __IO uint32_t DITHER_SEL          : 2;
    __IO uint32_t HEMP_TH             : 6;
    __IO uint32_t DACL_INVERSE        : 1;
    __IO uint32_t DACR_INVERSE        : 1;
    __IO uint32_t CHNL_IIR_SEL        : 8;
    __IO uint32_t CHNR_IIR_SEL        : 8;
} DEV_DAC_CFG0_Field;
/****DEV_DACCFG0 end****/

/***********************************CFG1***********************************/
typedef struct
{
    __IO uint32_t DACL_MIX_SOURCE     : 4;
    __IO uint32_t DACR_MIX_SOURCE     : 4;
    __IO uint32_t DACL_MIX_GAIN       : 2;
    __IO uint32_t DACR_MIX_GAIN       : 2;
    __IO uint32_t DBG_IN_EN           : 1;
    __IO uint32_t DBG_OUT_EN          : 1;
    __IO uint32_t DBG_CHN_SEL         : 1;
    uint32_t RESERVED0           : 1;
    __IO uint32_t DAC_VOL_L           : 6;
    uint32_t RESERVED1           : 2;
    __IO uint32_t DAC_VOL_R           : 6;
    uint32_t RESERVED2           : 2;
} DEV_DAC_CFG1_Field;
/****DEV_DACCFG1 end****/

/***********************************CTL***********************************/
typedef struct
{
    __IO uint32_t TX_EN               : 1;
    __IO uint32_t DMA_EN              : 1;
    __IO uint32_t TX_FIFO_RST         : 1;
    __IO uint32_t EQ_EN               : 1;
    __IO uint32_t ANC_EN              : 1;
    __IO uint32_t DRC_EN              : 1;
    __IO uint32_t DSD_EN              : 1;
    uint32_t RESERVED0           : 25;
} DEV_DAC_CTL_Field;
/****DEV_DACCTL end****/

/***********************************IE***********************************/
typedef struct
{
    __IO uint32_t TX_IRQ              : 1;
    __IO uint32_t TX_FIFO_OF          : 1;
    __IO uint32_t TX_FIFO_UF          : 1;
    uint32_t RESERVED0           : 29;
} DEV_DAC_IE_Field;
/****DEV_DACIE end****/

/***********************************PD***********************************/
typedef struct
{
    __IO uint32_t TX_IRQ              : 1;
    __IO uint32_t TX_FIFO_OF          : 1;
    __IO uint32_t TX_FIFO_UF          : 1;
    uint32_t RESERVED0           : 29;
} DEV_DAC_PD_Field;
/****DEV_DACPD end****/

/***********************************STA***********************************/
typedef struct
{
    __I  uint32_t TX_FIFO_WLVL        : 6;
    uint32_t RESERVED0           : 2;
    __I  uint32_t TX_FIFO_HEMP        : 1;
    __I  uint32_t TX_FIFO_EMPT        : 1;
    __I  uint32_t TX_FIFO_HFUL        : 1;
    __I  uint32_t TX_FIFO_FULL        : 1;
    uint32_t RESERVED1           : 20;
} DEV_DAC_STA_Field;
/****DEV_DACSTA end****/

/***********************************TBUF***********************************/
typedef struct
{
    __O  uint32_t TBUF                : 32;
} DEV_DAC_TBUF_Field;
/****DEV_DACTBUF end****/

/***********************************CFG2***********************************/
typedef struct
{
    __IO uint32_t CIC_SR_OUT          : 2;
    __IO uint32_t ANA_CLK_DIV         : 2;
    __IO uint32_t MONO_EN             : 1;
    __IO uint32_t DCB_EN              : 1;
    uint32_t RESERVED0           : 2;
    __IO uint32_t DSD_FMT_16BIT       : 1;
    __IO uint32_t DSD_FMT_BO          : 1;
    __IO uint32_t DSD_FMT_START       : 2;
    __IO uint32_t DAC_FMT_16BIT       : 1;
    __IO uint32_t DAC_FMT_USEHI       : 1;
    uint32_t RESERVED1           : 2;
    __IO uint32_t DSD_VOL_L           : 6;
    uint32_t RESERVED2           : 2;
    __IO uint32_t DSD_VOL_R           : 6;
    uint32_t RESERVED3           : 2;
} DEV_DAC_CFG2_Field;
/****DEV_DACCFG2 end****/

/***********************************DCB***********************************/
typedef struct
{
    __IO uint32_t DCB                 : 24;
    uint32_t RESERVED0           : 8;
} DEV_DAC_DCB_Field;
/****DEV_DACDCB end****/

/***********************************BIST_RM***********************************/
typedef struct
{
    __IO uint32_t RAM_RM              : 4;
    uint32_t RESERVED0           : 28;
} DEV_DAC_BIST_RM_Field;
/****DEV_DACBIST_RM end****/

/***********************************BIST_EN***********************************/
typedef struct
{
    __IO uint32_t RAM_EN              : 1;
    __IO uint32_t RAM_RME             : 1;
    __IO uint32_t RAM_LS              : 1;
    uint32_t RESERVED0           : 29;
} DEV_DAC_BIST_EN_Field;
/****DEV_DACBIST_EN end****/

/***********************************BIST_DONE***********************************/
typedef struct
{
    __I  uint32_t RAM_DONE            : 1;
    uint32_t RESERVED0           : 31;
} DEV_DAC_BIST_DONE_Field;
/****DEV_DACBIST_DONE end****/

/***********************************BIST_FAIL***********************************/
typedef struct
{
    __I  uint32_t RAM_FAIL            : 1;
    uint32_t RESERVED0           : 31;
} DEV_DAC_BIST_FAIL_Field;
/****DEV_DACBIST_FAIL end****/

/***********************************DA_CTL***********************************/
typedef struct
{
    __IO uint32_t DAC0_EN             : 1;
    __IO uint32_t DAC1_EN             : 1;
    __IO uint32_t DAC_CHOP_EN         : 1;
    __IO uint32_t DAC_GBW_SEL         : 1;
    __IO uint32_t DAC_CHOP_DIV        : 2;
    __IO uint32_t DAC_IBIAS_CTRL      : 2;
    __IO uint32_t DAC_NONOV           : 2;
    __IO uint32_t DAC_OPFB_PD         : 1;
    __IO uint32_t DAC_CLK_INVSEL      : 1;
    __IO uint32_t DAC_CLK_DLY         : 2;
    uint32_t RESERVED0           : 2;
    __IO uint32_t LO_VCMI_BYP         : 1;
    __IO uint32_t LO_VCMI_CHOP        : 1;
    __IO uint32_t DAC_RSVD_11         : 6;
    uint32_t RESERVED1           : 8;
} DEV_DAC_DA_CTL_Field;
/****DEV_DACDA_CTL end****/

/***********************************CP_CTL***********************************/
typedef struct
{
    __IO uint32_t CP_EN               : 1;
    __IO uint32_t CP_HS_EN            : 1;
    __IO uint32_t CP_CLK_SEL          : 1;
    __IO uint32_t CP_CLK_INV_SEL      : 1;
    __IO uint32_t CP_CLK_DIV          : 2;
    __IO uint32_t CP_CLK_NONOV        : 2;
    __IO uint32_t CP_CLK_DLY          : 2;
    uint32_t RESERVED0           : 22;
} DEV_DAC_CP_CTL_Field;
/****DEV_DACCP_CTL end****/

/***********************************HP_CTL0***********************************/
typedef struct
{
    __IO uint32_t HSPA0_EN            : 1;
    __IO uint32_t HSPA1_EN            : 1;
    __IO uint32_t HSPA0_DAC0_EN       : 1;
    __IO uint32_t HSPA0_DAC1_EN       : 1;
    __IO uint32_t HSPA0_MIX0_EN       : 1;
    __IO uint32_t HSPA0_MIX1_EN       : 1;
    __IO uint32_t HSPA1_DAC0_EN       : 1;
    __IO uint32_t HSPA1_DAC1_EN       : 1;
    __IO uint32_t HSPA1_MIX0_EN       : 1;
    __IO uint32_t HSPA1_MIX1_EN       : 1;
    __IO uint32_t HSPA_IBGM1_CTL      : 2;
    __IO uint32_t HSPA_IBGM2_CTL      : 2;
    __IO uint32_t HSPA_IBGM3_CTL      : 2;
    __IO uint32_t HSPA_IBIAS_CTL      : 2;
    __IO uint32_t HSCAL0_EN           : 1;
    __IO uint32_t HSCAL1_EN           : 1;
    __IO uint32_t GMIC0_EN            : 1;
    __IO uint32_t GMIC1_EN            : 1;
    __IO uint32_t HPFBSW0_EN          : 1;
    __IO uint32_t HPFBSW1_EN          : 1;
    __IO uint32_t GMIC0_S78_EN        : 1;
    __IO uint32_t GMIC1_S78_EN        : 1;
    uint32_t RESERVED0           : 6;
} DEV_DAC_HP_CTL0_Field;
/****DEV_DACHP_CTL0 end****/

/***********************************LO_CTL0***********************************/
typedef struct
{
    __IO uint32_t LO0_EN              : 1;
    __IO uint32_t LO0_DIFF_EN         : 1;
    __IO uint32_t LO1_EN              : 1;
    __IO uint32_t LO1_DIFF_EN         : 1;
    __IO uint32_t LO0_DAC0_EN         : 1;
    __IO uint32_t LO0_DAC1_EN         : 1;
    __IO uint32_t LO0_MIX0_EN         : 1;
    __IO uint32_t LO0_MIX1_EN         : 1;
    __IO uint32_t LO1_DAC0_EN         : 1;
    __IO uint32_t LO1_DAC1_EN         : 1;
    __IO uint32_t LO1_MIX0_EN         : 1;
    __IO uint32_t LO1_MIX1_EN         : 1;
    __IO uint32_t LO_CHOP_EN          : 1;
    __IO uint32_t LO_FASTSTUP         : 1;
    __IO uint32_t LO_VCMSTUP_CTL      : 2;
    __IO uint32_t LO_PD_STUP          : 1;
    __IO uint32_t LO_IBIAS_CTL        : 2;
    uint32_t RESERVED0           : 13;
} DEV_DAC_LO_CTL0_Field;
/****DEV_DACLO_CTL0 end****/

/***********************************LO_CTL1***********************************/
typedef struct
{
    __IO uint32_t LO0_RAMP_UP_EN      : 1;
    __IO uint32_t LO0_RAMP_DN_EN      : 1;
    __IO uint32_t LO1_RAMP_UP_EN      : 1;
    __IO uint32_t LO1_RAMP_DN_EN      : 1;
    uint32_t RESERVED0           : 12;
    __IO uint32_t RAMP_TIME           : 16;
} DEV_DAC_LO_CTL1_Field;
/****DEV_DACLO_CTL1 end****/

/***********************************LO_CTL2***********************************/
typedef struct
{
    __IO uint32_t HIGH_NUM            : 16;
    __IO uint32_t TOTAL_NUM           : 16;
} DEV_DAC_LO_CTL2_Field;
/****DEV_DACLO_CTL2 end****/

/***********************************HP_CTL1***********************************/
typedef struct
{
    __IO uint32_t DIV_CNT             : 8;
    uint32_t RESERVED0           : 24;
} DEV_DAC_HP_CTL1_Field;
/****DEV_DACHP_CTL1 end****/

/***********************************CHNL_IIR register***********************************/
typedef struct
{
    union
    {
        __IO    uint32_t    B0;                                      /* 0x0    Left. Channel IIR0 Coefficient B0 */
        DEV_DAC_HNL_IIRn_B0_Field    B0_f;
    };
    union
    {
        __IO    uint32_t    B1;                                      /* 0x4    Left. Channel IIR0 Coefficient B1 */
        DEV_DAC_HNL_IIRn_B1_Field    B1_f;
    };
    union
    {
        __IO    uint32_t    B2;                                      /* 0x8    Left. Channel IIR0 Coefficient B2 */
        DEV_DAC_HNL_IIRn_B2_Field    B2_f;
    };
    union
    {
        __IO    uint32_t    A1;                                      /* 0xc    Left. Channel IIR0 Coefficient A1 */
        DEV_DAC_HNL_IIRn_A1_Field    A1_f;
    };
    union
    {
        __IO    uint32_t    A2;                                      /* 0x10    Left. Channel IIR0 Coefficient A2 */
        DEV_DAC_HNL_IIRn_A2_Field    A2_f;
    };
    uint32_t    RESERVED0[59];
} CHNL_IIR_RegDef_f;
/****CHNL_IIR end****/

/***********************************CHNR_IIR register***********************************/
typedef struct
{
    union
    {
        __IO    uint32_t    B0;                                      /* 0x800    Left. Channel IIR2 Coefficient B0 */
        DEV_DAC_HNR_IIRn_B0_Field    B0_f;
    };
    union
    {
        __IO    uint32_t    B1;                                      /* 0x804    Left. Channel IIR2 Coefficient B1 */
        DEV_DAC_HNR_IIRn_B1_Field    B1_f;
    };
    union
    {
        __IO    uint32_t    B2;                                      /* 0x808    Left. Channel IIR2 Coefficient B2 */
        DEV_DAC_HNR_IIRn_B2_Field    B2_f;
    };
    union
    {
        __IO    uint32_t    A1;                                      /* 0x80c    Left. Channel IIR2 Coefficient A1 */
        DEV_DAC_HNR_IIRn_A1_Field    A1_f;
    };
    union
    {
        __IO    uint32_t    A2;                                      /* 0x810    Left. Channel IIR2 Coefficient A2 */
        DEV_DAC_HNR_IIRn_A2_Field    A2_f;
    };
    uint32_t    RESERVED0[59];
} CHNR_IIR_RegDef_f;
/****CHNR_IIR end****/

/***********************************DEV_DAC register***********************************/
typedef struct
{
    union
    {
        CHNL_IIR_RegDef_f    CHNL_IIR[7];                             /* 0x0    Left. Channel IIR0 Coefficient B0 */
    };
    union
    {
        __IO    uint32_t    CHNL_IIR7_B0;                            /* 0x700    Left. Channel IIR2 Coefficient B2 */
        DEV_DAC_HNL_IIR7_B0_Field    CHNL_IIR7_B0_f;
    };
    union
    {
        __IO    uint32_t    CHNL_IIR7_B1;                            /* 0x704    Left. Channel IIR2 Coefficient A2 */
        DEV_DAC_HNL_IIR7_B1_Field    CHNL_IIR7_B1_f;
    };
    union
    {
        __IO    uint32_t    CHNL_IIR7_B2;                            /* 0x708    Left. Channel IIR3 Coefficient B1 */
        DEV_DAC_HNL_IIR7_B2_Field    CHNL_IIR7_B2_f;
    };
    union
    {
        __IO    uint32_t    CHNL_IIR7_A1;                            /* 0x70c    Left. Channel IIR3 Coefficient A1 */
        DEV_DAC_HNL_IIR7_A1_Field    CHNL_IIR7_A1_f;
    };
    union
    {
        __IO    uint32_t    CHNL_IIR7_A2;                            /* 0x710    Left. Channel IIR3 Coefficient A2 */
        DEV_DAC_HNL_IIR7_A2_Field    CHNL_IIR7_A2_f;
    };
    uint32_t    RESERVED0[59];
    union
    {
        CHNR_IIR_RegDef_f    CHNR_IIR[7];                             /* 0x800    Left. Channel IIR4 Coefficient B0 */
    };
    union
    {
        __IO    uint32_t    CHNR_IIR7_B0;                            /* 0xf00    Left. Channel IIR5 Coefficient B2 */
        DEV_DAC_HNR_IIR7_B0_Field    CHNR_IIR7_B0_f;
    };
    union
    {
        __IO    uint32_t    CHNR_IIR7_B1;                            /* 0xf04    Left. Channel IIR5 Coefficient A1 */
        DEV_DAC_HNR_IIR7_B1_Field    CHNR_IIR7_B1_f;
    };
    union
    {
        __IO    uint32_t    CHNR_IIR7_B2;                            /* 0xf08    Left. Channel IIR5 Coefficient A2 */
        DEV_DAC_HNR_IIR7_B2_Field    CHNR_IIR7_B2_f;
    };
    union
    {
        __IO    uint32_t    CHNR_IIR7_A1;                            /* 0xf0c    Left. Channel IIR6 Coefficient B0 */
        DEV_DAC_HNR_IIR7_A1_Field    CHNR_IIR7_A1_f;
    };
    union
    {
        __IO    uint32_t    CHNR_IIR7_A2;                            /* 0xf10    Left. Channel IIR6 Coefficient B1 */
        DEV_DAC_HNR_IIR7_A2_Field    CHNR_IIR7_A2_f;
    };
    uint32_t    RESERVED1[28];
    union
    {
        __IO    uint32_t    DRC_LMTH;                                /* 0xf84    Left. Channel IIR6 Coefficient B2 */
        DEV_DAC_RC_LMTH_Field    DRC_LMTH_f;
    };
    union
    {
        __IO    uint32_t    DRC_SLOP;                                /* 0xf88    Left. Channel IIR6 Coefficient A1 */
        DEV_DAC_RC_SLOP_Field    DRC_SLOP_f;
    };
    union
    {
        __IO    uint32_t    DRC_PEAK_AT;                             /* 0xf8c    Left. Channel IIR6 Coefficient A2 */
        DEV_DAC_RC_PEAK_AT_Field    DRC_PEAK_AT_f;
    };
    union
    {
        __IO    uint32_t    DRC_PEAK_RT;                             /* 0xf90    Left. Channel IIR7 Coefficient B0 */
        DEV_DAC_RC_PEAK_RT_Field    DRC_PEAK_RT_f;
    };
    union
    {
        __IO    uint32_t    DRC_GAIN_AT;                             /* 0xf94    Left. Channel IIR7 Coefficient B1 */
        DEV_DAC_RC_GAIN_AT_Field    DRC_GAIN_AT_f;
    };
    union
    {
        __IO    uint32_t    DRC_GAIN_RT;                             /* 0xf98    Left. Channel IIR7 Coefficient B2 */
        DEV_DAC_RC_GAIN_RT_Field    DRC_GAIN_RT_f;
    };
    uint32_t    RESERVED2[9];
    union
    {
        __IO    uint32_t    DSD_COE_B1;                              /* 0xfc0    Left. Channel IIR7 Coefficient A1 */
        DEV_DAC_SD_COE_B1_Field    DSD_COE_B1_f;
    };
    union
    {
        __IO    uint32_t    DSD_COE_B2;                              /* 0xfc4    Left. Channel IIR7 Coefficient A2 */
        DEV_DAC_SD_COE_B2_Field    DSD_COE_B2_f;
    };
    union
    {
        __IO    uint32_t    DSD_COE_A1;                              /* 0xfc8    Right Channel IIR0 Coefficient B0 */
        DEV_DAC_SD_COE_A1_Field    DSD_COE_A1_f;
    };
    union
    {
        __IO    uint32_t    DSD_COE_A2;                              /* 0xfcc    Right Channel IIR0 Coefficient B1 */
        DEV_DAC_SD_COE_A2_Field    DSD_COE_A2_f;
    };
    union
    {
        __IO    uint32_t    DSD_COE_A3;                              /* 0xfd0    Right Channel IIR0 Coefficient B2 */
        DEV_DAC_SD_COE_A3_Field    DSD_COE_A3_f;
    };
    uint32_t    RESERVED3[11];
    union
    {
        __IO    uint32_t    CFG0;                                    /* 0x1000    Right Channel IIR0 Coefficient A1 */
        DEV_DAC_CFG0_Field    CFG0_f;
    };
    union
    {
        __IO    uint32_t    CFG1;                                    /* 0x1004    Right Channel IIR0 Coefficient A2 */
        DEV_DAC_CFG1_Field    CFG1_f;
    };
    union
    {
        __IO    uint32_t    CTL;                                     /* 0x1008    Right Channel IIR1 Coefficient B0 */
        DEV_DAC_CTL_Field    CTL_f;
    };
    union
    {
        __IO    uint32_t    IE;                                      /* 0x100c    Right Channel IIR1 Coefficient B1 */
        DEV_DAC_IE_Field    IE_f;
    };
    union
    {
        __IO    uint32_t    PD;                                      /* 0x1010    Right Channel IIR1 Coefficient B2 */
        DEV_DAC_PD_Field    PD_f;
    };
    union
    {
        __I     uint32_t    STA;                                     /* 0x1014    Right Channel IIR1 Coefficient A1 */
        DEV_DAC_STA_Field    STA_f;
    };
    union
    {
        __O     uint32_t    TBUF;                                    /* 0x1018    Right Channel IIR1 Coefficient A2 */
        DEV_DAC_TBUF_Field    TBUF_f;
    };
    union
    {
        __IO    uint32_t    CFG2;                                    /* 0x101c    Right Channel IIR2 Coefficient B0 */
        DEV_DAC_CFG2_Field    CFG2_f;
    };
    union
    {
        __IO    uint32_t    DCB;                                     /* 0x1020    Right Channel IIR2 Coefficient B1 */
        DEV_DAC_DCB_Field    DCB_f;
    };
    uint32_t    RESERVED4[1015];
    union
    {
        __IO    uint32_t    BIST_RM;                                 /* 0x2000    Right Channel IIR2 Coefficient B2 */
        DEV_DAC_BIST_RM_Field    BIST_RM_f;
    };
    union
    {
        __IO    uint32_t    BIST_EN;                                 /* 0x2004    Right Channel IIR2 Coefficient A1 */
        DEV_DAC_BIST_EN_Field    BIST_EN_f;
    };
    union
    {
        __I     uint32_t    BIST_DONE;                               /* 0x2008    Right Channel IIR2 Coefficient A2 */
        DEV_DAC_BIST_DONE_Field    BIST_DONE_f;
    };
    union
    {
        __I     uint32_t    BIST_FAIL;                               /* 0x200c    Right Channel IIR3 Coefficient B0 */
        DEV_DAC_BIST_FAIL_Field    BIST_FAIL_f;
    };
    uint32_t    RESERVED5[6140];
    union
    {
        __IO    uint32_t    DA_CTL;                                  /* 0x8000    Right Channel IIR3 Coefficient B1 */
        DEV_DAC_DA_CTL_Field    DA_CTL_f;
    };
    union
    {
        __IO    uint32_t    CP_CTL;                                  /* 0x8004    Right Channel IIR3 Coefficient B2 */
        DEV_DAC_CP_CTL_Field    CP_CTL_f;
    };
    union
    {
        __IO    uint32_t    HP_CTL0;                                 /* 0x8008    Right Channel IIR3 Coefficient A1 */
        DEV_DAC_HP_CTL0_Field    HP_CTL0_f;
    };
    union
    {
        __IO    uint32_t    LO_CTL0;                                 /* 0x800c    Right Channel IIR3 Coefficient A2 */
        DEV_DAC_LO_CTL0_Field    LO_CTL0_f;
    };
    union
    {
        __IO    uint32_t    LO_CTL1;                                 /* 0x8010    Right Channel IIR4 Coefficient B0 */
        DEV_DAC_LO_CTL1_Field    LO_CTL1_f;
    };
    union
    {
        __IO    uint32_t    LO_CTL2;                                 /* 0x8014    Right Channel IIR4 Coefficient B1 */
        DEV_DAC_LO_CTL2_Field    LO_CTL2_f;
    };
    union
    {
        __IO    uint32_t    HP_CTL1;                                 /* 0x8018    Right Channel IIR4 Coefficient B2 */
        DEV_DAC_HP_CTL1_Field    HP_CTL1_f;
    };
} DEV_DAC_RegDef_f;
/****DEV_DAC end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
