#ifndef __AON_AUDI_H__
#define __AON_AUDI_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************AUDI_ADC_CTL***********************************/
#define AON_AUDI_ADC_CTL_MADC0_RANGE_SIGNED                     (0x0UL<<15)
#define AON_AUDI_ADC_CTL_MADC0_RANGE_UNSIGNED                   (0x1UL<<15)
#define AON_AUDI_ADC_CTL_MADC0_RANGE_MASK                       (0x1UL<<15)
#define AON_AUDI_ADC_CTL_DCLK_SEL_NEGEDGE                       (0x0UL<<1)
#define AON_AUDI_ADC_CTL_DCLK_SEL_POSEDGE                       (0x1UL<<1)
#define AON_AUDI_ADC_CTL_DCLK_SEL_MASK                          (0x1UL<<1)
#define AON_AUDI_ADC_CTL_ADC_STA                                (0x1UL<<0)
/****AUDI_ADC_CTL end****/


/***********************************AUDI_DMIC_CTL***********************************/
#define AON_AUDI_DMIC_CTL_DMIC_EN_F_DISABLE                     (0x0UL<<6)
#define AON_AUDI_DMIC_CTL_DMIC_EN_F_ENABLE                      (0x1UL<<6)
#define AON_AUDI_DMIC_CTL_DMIC_EN_F_MASK                        (0x1UL<<6)
#define AON_AUDI_DMIC_CTL_PCM_RSTEN_RESET                       (0x0UL<<5)
#define AON_AUDI_DMIC_CTL_PCM_RSTEN_ENABLE                      (0x1UL<<5)
#define AON_AUDI_DMIC_CTL_PCM_RSTEN_MASK                        (0x1UL<<5)
#define AON_AUDI_DMIC_CTL_PCM_CLKEN_CLOCKDISABLE                (0x0UL<<4)
#define AON_AUDI_DMIC_CTL_PCM_CLKEN_CLOCKENABLE                 (0x1UL<<4)
#define AON_AUDI_DMIC_CTL_PCM_CLKEN_MASK                        (0x1UL<<4)
#define AON_AUDI_DMIC_CTL_DMIC_DELAY_0NS                        (0x0UL<<2)
#define AON_AUDI_DMIC_CTL_DMIC_DELAY_40NS                       (0x1UL<<2)
#define AON_AUDI_DMIC_CTL_DMIC_DELAY_80NS                       (0x2UL<<2)
#define AON_AUDI_DMIC_CTL_DMIC_DELAY_120NS                      (0x3UL<<2)
#define AON_AUDI_DMIC_CTL_DMIC_DELAY_MASK                       (0x3UL<<2)
#define AON_AUDI_DMIC_CTL_DMIC_MODE_SLAVE                       (0x0UL<<1)
#define AON_AUDI_DMIC_CTL_DMIC_MODE_MASTER                      (0x1UL<<1)
#define AON_AUDI_DMIC_CTL_DMIC_MODE_MASK                        (0x1UL<<1)
#define AON_AUDI_DMIC_CTL_DMIC_EN_DISABLE                       (0x0UL<<0)
#define AON_AUDI_DMIC_CTL_DMIC_EN_ENABLE                        (0x1UL<<0)
#define AON_AUDI_DMIC_CTL_DMIC_EN_MASK                          (0x1UL<<0)
/****AUDI_DMIC_CTL end****/


/***********************************AUDI_I2SRX_CTL***********************************/
#define AON_AUDI_I2SRX_CTL_INTER_SEPARATE                       (0x0UL<<4)
#define AON_AUDI_I2SRX_CTL_INTER_INTERLEAVE                     (0x1UL<<4)
#define AON_AUDI_I2SRX_CTL_INTER_MASK                           (0x1UL<<4)
#define AON_AUDI_I2SRX_CTL_WIDTH_16                             (0x0UL<<2)
#define AON_AUDI_I2SRX_CTL_WIDTH_20                             (0x1UL<<2)
#define AON_AUDI_I2SRX_CTL_WIDTH_24                             (0x2UL<<2)
#define AON_AUDI_I2SRX_CTL_WIDTH_32                             (0x3UL<<2)
#define AON_AUDI_I2SRX_CTL_WIDTH_MASK                           (0x3UL<<2)
#define AON_AUDI_I2SRX_CTL_MODE_SLAVE                           (0x0UL<<1)
#define AON_AUDI_I2SRX_CTL_MODE_MASTER                          (0x1UL<<1)
#define AON_AUDI_I2SRX_CTL_MODE_MASK                            (0x1UL<<1)
#define AON_AUDI_I2SRX_CTL_EN                                   (0x1UL<<0)
/****AUDI_I2SRX_CTL end****/


/***********************************AUDI_IE0***********************************/
#define AON_AUDI_IE0_FIFO1_OV                                   (0x1UL<<25)
#define AON_AUDI_IE0_FIFO0_OV                                   (0x1UL<<24)
#define AON_AUDI_IE0_VAD1_DET                                   (0x1UL<<23)
#define AON_AUDI_IE0_VAD0_DET                                   (0x1UL<<22)
#define AON_AUDI_IE0_UPD1_IE                                    (0x1UL<<19)
#define AON_AUDI_IE0_UPD0_IE                                    (0x1UL<<18)
#define AON_AUDI_IE0_VAD1_IE                                    (0x1UL<<17)
#define AON_AUDI_IE0_VAD0_IE                                    (0x1UL<<16)
#define AON_AUDI_IE0_WRAP1_IE                                   (0x1UL<<9)
#define AON_AUDI_IE0_WRAP0_IE                                   (0x1UL<<8)
#define AON_AUDI_IE0_SLOT1_IE                                   (0x1UL<<1)
#define AON_AUDI_IE0_SLOT0_IE                                   (0x1UL<<0)
/****AUDI_IE0 end****/


/***********************************AUDI_WKEN***********************************/
#define AON_AUDI_WKEN_FIFO1_OV                                  (0x1UL<<25)
#define AON_AUDI_WKEN_FIFO0_OV                                  (0x1UL<<24)
#define AON_AUDI_WKEN_VAD1_DET                                  (0x1UL<<23)
#define AON_AUDI_WKEN_VAD0_DET                                  (0x1UL<<22)
#define AON_AUDI_WKEN_UPD1_IE                                   (0x1UL<<19)
#define AON_AUDI_WKEN_UPD0_IE                                   (0x1UL<<18)
#define AON_AUDI_WKEN_VAD1_IE                                   (0x1UL<<17)
#define AON_AUDI_WKEN_VAD0_IE                                   (0x1UL<<16)
#define AON_AUDI_WKEN_WRAP1_IE                                  (0x1UL<<9)
#define AON_AUDI_WKEN_WRAP0_IE                                  (0x1UL<<8)
#define AON_AUDI_WKEN_SLOT1_IE                                  (0x1UL<<1)
#define AON_AUDI_WKEN_SLOT0_IE                                  (0x1UL<<0)
/****AUDI_WKEN end****/


/***********************************AUDI_PD***********************************/
#define AON_AUDI_PD_FIFO1_OV                                    (0x1UL<<25)
#define AON_AUDI_PD_FIFO0_OV                                    (0x1UL<<24)
#define AON_AUDI_PD_VAD1_DET                                    (0x1UL<<23)
#define AON_AUDI_PD_VAD0_DET                                    (0x1UL<<22)
#define AON_AUDI_PD_UPD1_PD                                     (0x1UL<<19)
#define AON_AUDI_PD_UPD0_PD                                     (0x1UL<<18)
#define AON_AUDI_PD_VAD1_PD                                     (0x1UL<<17)
#define AON_AUDI_PD_VAD0_PD                                     (0x1UL<<16)
#define AON_AUDI_PD_WRAP1_PD                                    (0x1UL<<9)
#define AON_AUDI_PD_WRAP0_PD                                    (0x1UL<<8)
#define AON_AUDI_PD_SLOT1_PD                                    (0x1UL<<1)
#define AON_AUDI_PD_SLOT0_PD                                    (0x1UL<<0)
/****AUDI_PD end****/


/***********************************AUDI_CHNn_CTL***********************************/
#define AON_AUDI_CHNn_CTL_DCB_VAL_MASK                          (0xffffUL<<16)
#define AON_AUDI_CHNn_CTL_CHN_RST_WORK                          (0x0UL<<15)
#define AON_AUDI_CHNn_CTL_CHN_RST_RESET                         (0x1UL<<15)
#define AON_AUDI_CHNn_CTL_CHN_RST_MASK                          (0x1UL<<15)
#define AON_AUDI_CHNn_CTL_SAMP_DIV_1                            (0x0UL<<12)
#define AON_AUDI_CHNn_CTL_SAMP_DIV_2                            (0x1UL<<12)
#define AON_AUDI_CHNn_CTL_SAMP_DIV_3                            (0x2UL<<12)
#define AON_AUDI_CHNn_CTL_SAMP_DIV_4                            (0x3UL<<12)
#define AON_AUDI_CHNn_CTL_SAMP_DIV_6                            (0x4UL<<12)
#define AON_AUDI_CHNn_CTL_SAMP_DIV_8                            (0x5UL<<12)
#define AON_AUDI_CHNn_CTL_SAMP_DIV_12                           (0x6UL<<12)
#define AON_AUDI_CHNn_CTL_SAMP_DIV_24                           (0x7UL<<12)
#define AON_AUDI_CHNn_CTL_SAMP_DIV_MASK                         (0x7UL<<12)
#define AON_AUDI_CHNn_CTL_DCB_IIR_1_256                         (0x0UL<<10)
#define AON_AUDI_CHNn_CTL_DCB_IIR_1_512                         (0x1UL<<10)
#define AON_AUDI_CHNn_CTL_DCB_IIR_1_1024                        (0x2UL<<10)
#define AON_AUDI_CHNn_CTL_DCB_IIR_1_2048                        (0x3UL<<10)
#define AON_AUDI_CHNn_CTL_DCB_IIR_MASK                          (0x3UL<<10)
#define AON_AUDI_CHNn_CTL_DCB_SEL_NO                            (0x0UL<<8)
#define AON_AUDI_CHNn_CTL_DCB_SEL_AUTO                          (0x1UL<<8)
#define AON_AUDI_CHNn_CTL_DCB_SEL_FIX                           (0x2UL<<8)
#define AON_AUDI_CHNn_CTL_DCB_SEL_MASK                          (0x3UL<<8)
#define AON_AUDI_CHNn_CTL_CHN_SEL_MADC0                         (0x0UL<<4)
#define AON_AUDI_CHNn_CTL_CHN_SEL_I2SRX0                        (0x4UL<<4)
#define AON_AUDI_CHNn_CTL_CHN_SEL_I2SRX1                        (0x5UL<<4)
#define AON_AUDI_CHNn_CTL_CHN_SEL_PDM0                          (0x8UL<<4)
#define AON_AUDI_CHNn_CTL_CHN_SEL_PCM0                          (0xcUL<<4)
#define AON_AUDI_CHNn_CTL_CHN_SEL_MASK                          (0xfUL<<4)
#define AON_AUDI_CHNn_CTL_FIFO_AUTO                             (0x1UL<<3)
#define AON_AUDI_CHNn_CTL_CHN_AUTO                              (0x1UL<<2)
#define AON_AUDI_CHNn_CTL_CHN_SAV                               (0x1UL<<1)
#define AON_AUDI_CHNn_CTL_CHN_STA                               (0x1UL<<0)
/****AUDI_CHNn_CTL end****/


/***********************************AUDI_CHNn_BASE***********************************/
#define AON_AUDI_CHNn_BASE_ADDR_MASK                            (0xffffffffUL<<0)
/****AUDI_CHNn_BASE end****/


/***********************************AUDI_CHNn_SIZE***********************************/
#define AON_AUDI_CHNn_SIZE_SLOT_NUM_MASK                        (0xffffUL<<16)
#define AON_AUDI_CHNn_SIZE_WORD_NUM_MASK                        (0xffffUL<<0)
/****AUDI_CHNn_SIZE end****/


/***********************************AUDI_CHNn_CNT***********************************/
#define AON_AUDI_CHNn_CNT_SLOT_CNT_MASK                         (0xffffUL<<16)
#define AON_AUDI_CHNn_CNT_WORD_CNT_MASK                         (0xffffUL<<0)
/****AUDI_CHNn_CNT end****/


/***********************************AUDI_CHNn_GAIN***********************************/
#define AON_AUDI_CHNn_GAIN_1_16                                 (0x0UL<<0)
#define AON_AUDI_CHNn_GAIN_1_8                                  (0x1UL<<0)
#define AON_AUDI_CHNn_GAIN_1_4                                  (0x2UL<<0)
#define AON_AUDI_CHNn_GAIN_1_2                                  (0x3UL<<0)
#define AON_AUDI_CHNn_GAIN_1                                    (0x4UL<<0)
#define AON_AUDI_CHNn_GAIN_2                                    (0x5UL<<0)
#define AON_AUDI_CHNn_GAIN_4                                    (0x6UL<<0)
#define AON_AUDI_CHNn_GAIN_8                                    (0x7UL<<0)
#define AON_AUDI_CHNn_GAIN_MASK                                 (0x7UL<<0)
/****AUDI_CHNn_GAIN end****/


/***********************************AUDI_VADn_CTL***********************************/
#define AON_AUDI_VADn_CTL_NUM_MASK                              (0xfUL<<4)
#define AON_AUDI_VADn_CTL_MODE_PWR                              (0x0UL<<1)
#define AON_AUDI_VADn_CTL_MODE_ACR                              (0x1UL<<1)
#define AON_AUDI_VADn_CTL_MODE_PWR_AND_ACR                      (0x2UL<<1)
#define AON_AUDI_VADn_CTL_MODE_PWR_OR_ACR                       (0x3UL<<1)
#define AON_AUDI_VADn_CTL_MODE_MASK                             (0x3UL<<1)
#define AON_AUDI_VADn_CTL_EN                                    (0x1UL<<0)
/****AUDI_VADn_CTL end****/


/***********************************AUDI_VADn_CFG0***********************************/
#define AON_AUDI_VADn_CFG0_PWR_THD_MASK                         (0x3ffffffUL<<0)
/****AUDI_VADn_CFG0 end****/


/***********************************AUDI_VADn_CFG1***********************************/
#define AON_AUDI_VADn_CFG1_ACR_MODE_DIFFERENCE_CROSS            (0x0UL<<20)
#define AON_AUDI_VADn_CFG1_ACR_MODE_DIFFERENCEONLY              (0x1UL<<20)
#define AON_AUDI_VADn_CFG1_ACR_MODE_MASK                        (0x1UL<<20)
#define AON_AUDI_VADn_CFG1_ACR_SPD_MASK                         (0xfUL<<16)
#define AON_AUDI_VADn_CFG1_ACR_THD_MASK                         (0xffffUL<<0)
/****AUDI_VADn_CFG1 end****/


/***********************************AUDI_VADn_CFG2***********************************/
#define AON_AUDI_VADn_CFG2_ACR_WGH1_MASK                        (0xfUL<<28)
#define AON_AUDI_VADn_CFG2_ACR_WGH0_MASK                        (0xfUL<<24)
#define AON_AUDI_VADn_CFG2_ACR_LVL2_MASK                        (0xffUL<<16)
#define AON_AUDI_VADn_CFG2_ACR_LVL1_MASK                        (0xffUL<<8)
#define AON_AUDI_VADn_CFG2_ACR_LVL0_MASK                        (0xffUL<<0)
/****AUDI_VADn_CFG2 end****/


/***********************************AUDI_VADn_PWR***********************************/
#define AON_AUDI_VADn_PWR_VAD_PWR_MASK                          (0x3ffffffUL<<0)
/****AUDI_VADn_PWR end****/


/***********************************AUDI_VADn_ACR***********************************/
#define AON_AUDI_VADn_ACR_ACR_SCO_MASK                          (0xfUL<<8)
#define AON_AUDI_VADn_ACR_ACR_CNT_MASK                          (0xffUL<<0)
/****AUDI_VADn_ACR end****/


/***********************************AUDI_DBG_CTL***********************************/
#define AON_AUDI_DBG_CTL_EN                                     (0x1UL<<0)
/****AUDI_DBG_CTL end****/


/***********************************AUDI_BIST_TEST***********************************/
#define AON_AUDI_BIST_TEST_TEST                                 (0x1UL<<0)
/****AUDI_BIST_TEST end****/


/***********************************AUDI_BIST_DONE***********************************/
#define AON_AUDI_BIST_DONE_DONE                                 (0x1UL<<0)
/****AUDI_BIST_DONE end****/


/***********************************AUDI_BIST_FAIL***********************************/
#define AON_AUDI_BIST_FAIL_FAIL                                 (0x1UL<<0)
/****AUDI_BIST_FAIL end****/


/***********************************AUDI_CHN register***********************************/
typedef struct
{
    __IO    uint32_t    CTL;                                     /* 0x100    Channel0 Control */
    __IO    uint32_t    BASE;                                    /* 0x104    Channel0 Base */
    __IO    uint32_t    SIZE;                                    /* 0x108    Channel0 Size */
    __I     uint32_t    CNT;                                     /* 0x10c    Channel0 Counter */
    __IO    uint32_t    GAIN;                                    /* 0x110    Channel0 Gain */
    uint32_t    RESERVED0[3];
} AUDI_CHN_RegDef;
/****AUDI_CHN end****/

/***********************************AUDI_VAD register***********************************/
typedef struct
{
    __IO    uint32_t    CTL;                                     /* 0x200    Channel0 Size */
    __IO    uint32_t    CFG0;                                    /* 0x204    Channel0 Gain */
    __IO    uint32_t    CFG1;                                    /* 0x208    Channel1 Base */
    __IO    uint32_t    CFG2;                                    /* 0x20c    Channel1 Counter */
    __I     uint32_t    PWR;                                     /* 0x210    Channel1 Gain */
    __I     uint32_t    ACR;                                     /* 0x214    VAD0 Control */
    uint32_t    RESERVED0[2];
} AUDI_VAD_RegDef;
/****AUDI_VAD end****/

/***********************************AON_AUDI register***********************************/
typedef struct
{
    __IO    uint32_t    ADC_CTL;                                 /* 0x0    ADC Control */
    uint32_t    RESERVED0[3];
    __IO    uint32_t    DMIC_CTL;                                /* 0x10    DMIC Control */
    uint32_t    RESERVED1[3];
    __IO    uint32_t    I2SRX_CTL;                               /* 0x20    I2SRX Control */
    uint32_t    RESERVED2[23];
    __IO    uint32_t    IE0;                                     /* 0x80    Audio Input Interrupt Enable */
    __IO    uint32_t    WKEN;                                    /* 0x84    Audio Input Wakeup Enable */
    __IO    uint32_t    PD;                                      /* 0x88    Audio Input Interrupt Pending */
    uint32_t    RESERVED3[29];
    AUDI_CHN_RegDef    CHN[2];                                  /* 0x100    Channel0 Control */
    uint32_t    RESERVED4[48];
    AUDI_VAD_RegDef    VAD[2];                                  /* 0x200    Channel1 Base */
    uint32_t    RESERVED5[48];
    __IO    uint32_t    DBG_CTL;                                 /* 0x300    VAD0 Config0 */
    uint32_t    RESERVED6[63];
    __IO    uint32_t    BIST_TEST;                               /* 0x400    VAD0 Config2 */
    __IO    uint32_t    BIST_DONE;                               /* 0x404    VAD1 Average Cross Rate */
    __IO    uint32_t    BIST_FAIL;                               /* 0x408    VAD1 Control */
} AON_AUDI_RegDef;
/****AON_AUDI end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
