#ifndef __DEV_IICN_H__
#define __DEV_IICN_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************IIC_CFG***********************************/
#define DEV_IICn_CFG_IIC_EN_DISABLE                             (0x0UL<<16)
#define DEV_IICn_CFG_IIC_EN_ENABLE                              (0x1UL<<16)
#define DEV_IICn_CFG_IIC_EN_MASK                                (0x1UL<<16)
#define DEV_IICn_CFG_DIV_COE(clock,baud_rate)                   ((((clock)/2/(baud_rate)))<<8)
#define DEV_IICn_CFG_DIV_COE_MASK                               (0xffUL<<8)
#define DEV_IICn_CFG_SLV_ADDR_MASK                              (0x7fUL<<1)
#define DEV_IICn_CFG_MODE_MASTER                                (0x0UL<<0)
#define DEV_IICn_CFG_MODE_SLAVE                                 (0x1UL<<0)
#define DEV_IICn_CFG_MODE_MASK                                  (0x1UL<<0)
/****IIC_CFG end****/


/***********************************IIC_CTL***********************************/
#define DEV_IICn_CTL_CMD_RELEASEBUS                             (0x0UL<<12)
#define DEV_IICn_CTL_CMD_STARTCMD                               (0x1UL<<12)
#define DEV_IICn_CTL_CMD_STOPCMD                                (0x2UL<<12)
#define DEV_IICn_CTL_CMD_RESTARTCMD                             (0x3UL<<12)
#define DEV_IICn_CTL_CMD_MASK                                   (0x3UL<<12)
#define DEV_IICn_CTL_TX_ACK_ACK                                 (0x0UL<<8)
#define DEV_IICn_CTL_TX_ACK_NACK                                (0x1UL<<8)
#define DEV_IICn_CTL_TX_ACK_MASK                                (0x1UL<<8)
#define DEV_IICn_CTL_TX_DAT_MASK                                (0xffUL<<0)
/****IIC_CTL end****/


/***********************************IIC_IE***********************************/
#define DEV_IICn_IE_BUS_ERR                                     (0x1UL<<4)
#define DEV_IICn_IE_START_DET                                   (0x1UL<<3)
#define DEV_IICn_IE_NACK_DET                                    (0x1UL<<2)
#define DEV_IICn_IE_BYTE_END                                    (0x1UL<<1)
#define DEV_IICn_IE_STOP_DET                                    (0x1UL<<0)
/****IIC_IE end****/


/***********************************IIC_PD***********************************/
#define DEV_IICn_PD_BUS_ERR                                     (0x1UL<<4)
#define DEV_IICn_PD_START_DET                                   (0x1UL<<3)
#define DEV_IICn_PD_NACK_DET                                    (0x1UL<<2)
#define DEV_IICn_PD_BYTE_END                                    (0x1UL<<1)
#define DEV_IICn_PD_STOP_DET                                    (0x1UL<<0)
/****IIC_PD end****/


/***********************************IIC_STA***********************************/
#define DEV_IICn_STA_RX_BUF_FULL_EMPTY                          (0x0UL<<5)
#define DEV_IICn_STA_RX_BUF_FULL_FULL                           (0x1UL<<5)
#define DEV_IICn_STA_RX_BUF_FULL_MASK                           (0x1UL<<5)
#define DEV_IICn_STA_TX_BUF_FULL_EMPTY                          (0x0UL<<4)
#define DEV_IICn_STA_TX_BUF_FULL_FULL                           (0x1UL<<4)
#define DEV_IICn_STA_TX_BUF_FULL_MASK                           (0x1UL<<4)
#define DEV_IICn_STA_ADDR_VALID                                 (0x1UL<<3)
#define DEV_IICn_STA_RW_FLAG_MWR_SRD                            (0x0UL<<2)
#define DEV_IICn_STA_RW_FLAG_SWR_MRD                            (0x1UL<<2)
#define DEV_IICn_STA_RW_FLAG_MASK                               (0x1UL<<2)
#define DEV_IICn_STA_RX_ACK_ACK                                 (0x0UL<<1)
#define DEV_IICn_STA_RX_ACK_NACK                                (0x1UL<<1)
#define DEV_IICn_STA_RX_ACK_MASK                                (0x1UL<<1)
#define DEV_IICn_STA_BUSY_IDLE                                  (0x0UL<<0)
#define DEV_IICn_STA_BUSY_BUSY                                  (0x1UL<<0)
#define DEV_IICn_STA_BUSY_MASK                                  (0x1UL<<0)
/****IIC_STA end****/


/***********************************IIC_RX_DAT***********************************/
#define DEV_IICn_RX_DAT_MASK                                    (0xffUL<<0)
/****IIC_RX_DAT end****/


/***********************************DEV_IICn register***********************************/
typedef struct
{

    __IO    uint32_t    CFG;                                     /* 0x0    IIC Configure */
    __IO    uint32_t    CTL;                                     /* 0x4    IIC Control */
    __IO    uint32_t    IE;                                      /* 0x8    IIC Interrupt Enable */
    __IO    uint32_t    PD;                                      /* 0xc    IIC Interrupt Pending */
    __I     uint32_t    STA;                                     /* 0x10    IIC Status */
    __I     uint32_t    RX_DAT;                                  /* 0x14    IIC Rx Data(FIFO) */
} DEV_IICn_RegDef;
/****DEV_IICn end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
