#ifndef __DEV_RMU_H__
#define __DEV_RMU_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************RMU_RSTEN0***********************************/
#define DEV_RMU_RSTEN0_MPU                                      (0x1UL<<30)
#define DEV_RMU_RSTEN0_UART3                                    (0x1UL<<29)
#define DEV_RMU_RSTEN0_CAMERA                                   (0x1UL<<28)
#define DEV_RMU_RSTEN0_AON                                      (0x1UL<<27)
#define DEV_RMU_RSTEN0_UDSP                                     (0x1UL<<26)
#define DEV_RMU_RSTEN0_NPU                                      (0x1UL<<25)
#define DEV_RMU_RSTEN0_SRC                                      (0x1UL<<24)
#define DEV_RMU_RSTEN0_DAC                                      (0x1UL<<23)
#define DEV_RMU_RSTEN0_ADC                                      (0x1UL<<22)
#define DEV_RMU_RSTEN0_USB                                      (0x1UL<<20)
#define DEV_RMU_RSTEN0_SDC                                      (0x1UL<<19)
#define DEV_RMU_RSTEN0_PWM                                      (0x1UL<<18)
#define DEV_RMU_RSTEN0_IRTX                                     (0x1UL<<17)
#define DEV_RMU_RSTEN0_IRRX                                     (0x1UL<<16)
#define DEV_RMU_RSTEN0_ASI1                                     (0x1UL<<15)
#define DEV_RMU_RSTEN0_ASI0                                     (0x1UL<<14)
#define DEV_RMU_RSTEN0_I2C1                                     (0x1UL<<13)
#define DEV_RMU_RSTEN0_I2C0                                     (0x1UL<<12)
#define DEV_RMU_RSTEN0_UART2                                    (0x1UL<<11)
#define DEV_RMU_RSTEN0_UART1                                    (0x1UL<<10)
#define DEV_RMU_RSTEN0_UART0                                    (0x1UL<<9)
#define DEV_RMU_RSTEN0_SPI1                                     (0x1UL<<8)
#define DEV_RMU_RSTEN0_SPI0                                     (0x1UL<<7)
#define DEV_RMU_RSTEN0_TICK                                     (0x1UL<<6)
#define DEV_RMU_RSTEN0_TIMER                                    (0x1UL<<5)
#define DEV_RMU_RSTEN0_EINT                                     (0x1UL<<4)
#define DEV_RMU_RSTEN0_ASU                                      (0x1UL<<3)
#define DEV_RMU_RSTEN0_EFUSE                                    (0x1UL<<2)
#define DEV_RMU_RSTEN0_GPIO                                     (0x1UL<<1)
#define DEV_RMU_RSTEN0_DMA                                      (0x1UL<<0)
/****RMU_RSTEN0 end****/


/***********************************RMU_RSTEN1***********************************/
#define DEV_RMU_RSTEN1_PSRAM                                    (0x1UL<<15)
#define DEV_RMU_RSTEN1_MEM_BUS                                  (0x1UL<<14)
#define DEV_RMU_RSTEN1_HST_BUS                                  (0x1UL<<13)
#define DEV_RMU_RSTEN1_DEV_BUS                                  (0x1UL<<12)
#define DEV_RMU_RSTEN1_RAM7                                     (0x1UL<<11)
#define DEV_RMU_RSTEN1_RAM6                                     (0x1UL<<10)
#define DEV_RMU_RSTEN1_RAM5                                     (0x1UL<<9)
#define DEV_RMU_RSTEN1_RAM4                                     (0x1UL<<8)
#define DEV_RMU_RSTEN1_RAM3                                     (0x1UL<<7)
#define DEV_RMU_RSTEN1_RAM2                                     (0x1UL<<6)
#define DEV_RMU_RSTEN1_RAM1                                     (0x1UL<<5)
#define DEV_RMU_RSTEN1_RAM0                                     (0x1UL<<4)
#define DEV_RMU_RSTEN1_CACHE                                    (0x1UL<<3)
#define DEV_RMU_RSTEN1_NORC                                     (0x1UL<<2)
#define DEV_RMU_RSTEN1_SYS                                      (0x1UL<<1)
#define DEV_RMU_RSTEN1_CPU                                      (0x1UL<<0)
/****RMU_RSTEN1 end****/


/***********************************RMU_CPUVEC***********************************/
#define DEV_RMU_CPUVEC_BOOT_ADDR_MASK                           (0xffffffffUL<<0)
/****RMU_CPUVEC end****/


/***********************************RMU_WDOG***********************************/
#define DEV_RMU_WDOG_WDOG_PD                                    (0x1UL<<10)
#define DEV_RMU_WDOG_DEFER_TIME_10MS                            (0x0UL<<8)
#define DEV_RMU_WDOG_DEFER_TIME_125MS                           (0x1UL<<8)
#define DEV_RMU_WDOG_DEFER_TIME_250MS                           (0x2UL<<8)
#define DEV_RMU_WDOG_DEFER_TIME_500MS                           (0x3UL<<8)
#define DEV_RMU_WDOG_DEFER_TIME_MASK                            (0x3UL<<8)
#define DEV_RMU_WDOG_DEFER_EN                                   (0x1UL<<7)
#define DEV_RMU_WDOG_WDOG_TIME_10MS                             (0x0UL<<4)
#define DEV_RMU_WDOG_WDOG_TIME_125MS                            (0x1UL<<4)
#define DEV_RMU_WDOG_WDOG_TIME_250MS                            (0x2UL<<4)
#define DEV_RMU_WDOG_WDOG_TIME_500MS                            (0x3UL<<4)
#define DEV_RMU_WDOG_WDOG_TIME_1S                               (0x4UL<<4)
#define DEV_RMU_WDOG_WDOG_TIME_2S                               (0x5UL<<4)
#define DEV_RMU_WDOG_WDOG_TIME_4S                               (0x6UL<<4)
#define DEV_RMU_WDOG_WDOG_TIME_8S                               (0x7UL<<4)
#define DEV_RMU_WDOG_WDOG_TIME_MASK                             (0x7UL<<4)
#define DEV_RMU_WDOG_RESET_EN                                   (0x1UL<<3)
#define DEV_RMU_WDOG_IRQ_EN                                     (0x1UL<<2)
#define DEV_RMU_WDOG_WDOG_CLR                                   (0x1UL<<1)
#define DEV_RMU_WDOG_WDOG_EN_DISABLE                            (0x0UL<<0)
#define DEV_RMU_WDOG_WDOG_EN_ENABLE                             (0x1UL<<0)
#define DEV_RMU_WDOG_WDOG_EN_MASK                               (0x1UL<<0)
/****RMU_WDOG end****/


/***********************************RMU_BOOT***********************************/
#define DEV_RMU_BOOT_JTAG_WIRE_4WIRE                            (0x0UL<<26)
#define DEV_RMU_BOOT_JTAG_WIRE_2WIRE                            (0x1UL<<26)
#define DEV_RMU_BOOT_JTAG_WIRE_MASK                             (0x1UL<<26)
#define DEV_RMU_BOOT_NOR_MODE_UNCA                              (0x0UL<<25)
#define DEV_RMU_BOOT_NOR_MODE_CACHE                             (0x1UL<<25)
#define DEV_RMU_BOOT_NOR_MODE_MASK                              (0x1UL<<25)
#define DEV_RMU_BOOT_FIX_MODE_NOR                               (0x0UL<<24)
#define DEV_RMU_BOOT_FIX_MODE_ILM                               (0x1UL<<24)
#define DEV_RMU_BOOT_FIX_MODE_MASK                              (0x1UL<<24)
#define DEV_RMU_BOOT_VEC_MODE_FIX                               (0x0UL<<23)
#define DEV_RMU_BOOT_VEC_MODE_PIN                               (0x1UL<<23)
#define DEV_RMU_BOOT_VEC_MODE_MASK                              (0x1UL<<23)
#define DEV_RMU_BOOT_JTAG_POL_LEVEL                             (0x0UL<<22)
#define DEV_RMU_BOOT_JTAG_POL_EDGE                              (0x1UL<<22)
#define DEV_RMU_BOOT_JTAG_POL_MASK                              (0x1UL<<22)
#define DEV_RMU_BOOT_CPU_BOOT                                   (0x1UL<<21)
#define DEV_RMU_BOOT_PGM_SEL_MFP0                               (0x0UL<<18)
#define DEV_RMU_BOOT_PGM_SEL_MFP1                               (0x1UL<<18)
#define DEV_RMU_BOOT_PGM_SEL_MASK                               (0x1UL<<18)
#define DEV_RMU_BOOT_PGM_SWT                                    (0x1UL<<17)
#define DEV_RMU_BOOT_PGM_SOF                                    (0x1UL<<15)
#define DEV_RMU_BOOT_PGM_KEY                                    (0x1UL<<14)
#define DEV_RMU_BOOT_PGM_HRD                                    (0x1UL<<13)
#define DEV_RMU_BOOT_PGM_EN                                     (0x1UL<<12)
#define DEV_RMU_BOOT_JTAG_RST_MEM                               (0x1UL<<11)
#define DEV_RMU_BOOT_JTAG_RST_GPIO                              (0x1UL<<10)
#define DEV_RMU_BOOT_JTAG_RST_DEV                               (0x1UL<<9)
#define DEV_RMU_BOOT_JTAG_RST_CPU                               (0x1UL<<8)
#define DEV_RMU_BOOT_JTAG_SEL_DISABLE                           (0x0UL<<6)
#define DEV_RMU_BOOT_JTAG_SEL_MFP1                              (0x1UL<<6)
#define DEV_RMU_BOOT_JTAG_SEL_MFP2                              (0x2UL<<6)
#define DEV_RMU_BOOT_JTAG_SEL_MFP3                              (0x3UL<<6)
#define DEV_RMU_BOOT_JTAG_SEL_MASK                              (0x3UL<<6)
#define DEV_RMU_BOOT_JTAG_SWT                                   (0x1UL<<5)
#define DEV_RMU_BOOT_BOOT_SEL_NORMFP0                           (0x0UL<<3)
#define DEV_RMU_BOOT_BOOT_SEL_NORMFP1                           (0x1UL<<3)
#define DEV_RMU_BOOT_BOOT_SEL_NORMFP2                           (0x2UL<<3)
#define DEV_RMU_BOOT_BOOT_SEL_NORMFP3                           (0x3UL<<3)
#define DEV_RMU_BOOT_BOOT_SEL_MASK                              (0x3UL<<3)
#define DEV_RMU_BOOT_BOOT_SWT                                   (0x1UL<<2)
#define DEV_RMU_BOOT_RE_BOOT                                    (0x1UL<<1)
#define DEV_RMU_BOOT_BOOT_EN_DISABLE                            (0x0UL<<0)
#define DEV_RMU_BOOT_BOOT_EN_ENABLE                             (0x1UL<<0)
#define DEV_RMU_BOOT_BOOT_EN_MASK                               (0x1UL<<0)
/****RMU_BOOT end****/


/***********************************RMU_PD***********************************/
#define DEV_RMU_PD_BOOT                                         (0x1UL<<4)
#define DEV_RMU_PD_WDOG                                         (0x1UL<<3)
#define DEV_RMU_PD_P_RSTN                                       (0x1UL<<2)
#define DEV_RMU_PD_ONOFF                                        (0x1UL<<1)
#define DEV_RMU_PD_POWER                                        (0x1UL<<0)
/****RMU_PD end****/


/***********************************DEV_RMU register***********************************/
typedef struct
{

    __IO    uint32_t    RSTEN0;                                  /* 0x0    Reset Enable */
    __IO    uint32_t    RSTEN1;                                  /* 0x4    Reset Enable */
    uint32_t    RESERVED0[3];
    __IO    uint32_t    CPUVEC;                                  /* 0x14    CPU Reset Vector */
    uint32_t    RESERVED1[2];
    __IO    uint32_t    WDOG;                                    /* 0x20    Watch Dog Control */
    __IO    uint32_t    BOOT;                                    /* 0x24    Boot Control */
    uint32_t    RESERVED2[6];
    __IO    uint32_t    PD;                                      /* 0x40    RMU Pending */
} DEV_RMU_RegDef;
/****DEV_RMU end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
