/**
* @file         mm_card.c
* @brief        emmc卡驱动
* @details      emmc卡驱动
* @author       涂龙
* @date         2022-01-25 09:18
* @version      V0.0
* @copyright    Copyright (c) 2017-2022  SpaceTouch Inc.
*/
#ifndef __MMC_H__
#define __MMC_H__


#include "hal_memory_card.h"

//超时检测宏开关
#define DEV_MMC_TIME_OUT_CHECK      1
//sdc超时时长设置
#define DEV_MMC_TIME_OUT_TIME       100UL//ms  500

#define MMC_CMD(n)  (n)
#define MMC_ACMD(n) (n)



typedef MEMORY_CARD_Info *MMC_Info;





/** mmc reg bit fild define */
#define DEV_MMC_CTRL_ENABLE_OD_PULLUP               (1UL << 24)
#define DEV_MMC_CTRL_CARD_VOLTAGE_B(n)              (((n) & 0xfUL) << 20UL)
#define DEV_MMC_CTRL_CARD_VOLTAGE_B_MASK            (0xfUL << 20)
#define DEV_MMC_CTRL_CARD_VOLTAGE_A(n)              (((n) & 0xfUL) << 16UL)
#define DEV_MMC_CTRL_CARD_VOLTAGE_A_MASK            (0xfUL << 16UL)
#define DEV_MMC_CTRL_CEATA_DEV_INT_STS              (1UL << 11UL)
#define DEV_MMC_CTRL_SEND_AUTO_STOP_CCSD            (1UL << 10UL)
#define DEV_MMC_CTRL_SEND_CCSD                      (1UL << 9UL)
#define DEV_MMC_CTRL_ABORT_READ_DATA                (1UL << 8UL)
#define DEV_MMC_CTRL_SEND_IRQ_RESPONSE              (1UL << 7UL)
#define DEV_MMC_CTRL_READ_WAIT                      (1UL << 6UL)
#define DEV_MMC_CTRL_DMA_ENABLE                     (1UL << 5UL)
#define DEV_MMC_CTRL_INT_ENABLE                     (1UL << 4UL)
#define DEV_MMC_CTRL_DMA_RESET                      (1UL << 2UL)
#define DEV_MMC_CTRL_FIFO_RESET                     (1UL << 1UL)
#define DEV_MMC_CTRL_CONTROLLER_RESET               (1UL << 0UL)

#define DEV_MMC_CMD_START_CMD                       (1UL << 31UL)
#define DEV_MMC_CMD_USE_HOLD_REG                    (1UL << 29UL)
#define DEV_MMC_CMD_VOLT_SWITCH                     (1UL << 28UL)
#define DEV_MMC_CMD_BOOT_MODE                       (1UL << 27UL)
#define DEV_MMC_CMD_DISABLE_BOOT                    (1UL << 26UL)
#define DEV_MMC_CMD_EXPECT_BOOT_ACK                 (1UL << 25UL)
#define DEV_MMC_CMD_ENABLE_BOOT                     (1UL << 24UL)
#define DEV_MMC_CMD_CCS_EXPECTED                    (1UL << 23UL)
#define DEV_MMC_CMD_READ_CEATA_DEVICE               (1UL << 22UL)
#define DEV_MMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY     (1UL << 21UL)
#define DEV_MMC_CMD_CARD_NUMBER(n)                  (((n) & 0x1fUL) << 16UL)
#define DEV_MMC_CMD_SEND_INITIALIZATION             (1UL << 15UL)
#define DEV_MMC_CMD_STOP_ABORT_CMD                  (1UL << 14UL)
#define DEV_MMC_CMD_WAIT_PRVDATA_COMPLETE           (1UL << 13UL)
#define DEV_MMC_CMD_SEND_AUTO_STOP                  (1UL << 12UL)
#define DEV_MMC_CMD_TRANSFER_MODE                   (1UL << 11UL)
#define DEV_MMC_CMD_READ_WRITE                      (1UL << 10UL)
#define DEV_MMC_CMD_DATA_EXPECTED                   (1UL << 9UL)
#define DEV_MMC_CMD_CHECK_RESPONSE_CRC              (1UL << 8UL)
#define DEV_MMC_CMD_RESPONSE_LENGTH                 (1UL << 7UL)
#define DEV_MMC_CMD_RESPONSE_EXPECT                 (1UL << 6UL)
#define DEV_MMC_CMD_CMD_INDEX(n)                    (((n) & 0x3fUL) << 0)

#define DEV_MMC_RINTSTS_EBE                         (1UL << 15UL)
#define DEV_MMC_RINTSTS_ACD                         (1UL << 14UL)
#define DEV_MMC_RINTSTS_SBE_BCI                     (1UL << 13UL)
#define DEV_MMC_RINTSTS_HLE                         (1UL << 12UL)
#define DEV_MMC_RINTSTS_FRUN                        (1UL << 11UL)
#define DEV_MMC_RINTSTS_HTO                         (1UL << 10UL)
#define DEV_MMC_RINTSTS_VOLV_SWITCH                 (1UL << 10UL)
#define DEV_MMC_RINTSTS_DRTO_BDS                    (1UL << 9UL)
#define DEV_MMC_RINTSTS_RTO_BAR                     (1UL << 8UL)
#define DEV_MMC_RINTSTS_DCRC                        (1UL << 7UL)
#define DEV_MMC_RINTSTS_RCRC                        (1UL << 6UL)
#define DEV_MMC_RINTSTS_RXDR                        (1UL << 5UL)
#define DEV_MMC_RINTSTS_TXDR                        (1UL << 4UL)
#define DEV_MMC_RINTSTS_DTO                         (1UL << 3UL)
#define DEV_MMC_RINTSTS_CD                          (1UL << 2UL)
#define DEV_MMC_RINTSTS_RE                          (1UL << 1UL)
#define DEV_MMC_RINTSTS_CDT                         (1UL << 0UL)

#define DEV_MMC_RINTSTS_SDIO_INTERRUPT              (0xffff0000UL)
#define DEV_MMC_RINTSTS_INT_STATUS_MASK             (0x0000ffffUL)

#define DEV_MMC_STATUS_DMA_REQ                      (1UL << 31UL)
#define DEV_MMC_STATUS_DMA_ACK                      (1UL << 30UL)
#define DEV_MMC_STATUS_FIFO_COUNT_MASK              (0x1fffUL << 17UL)
#define DEV_MMC_STATUS_RESPONSE_INDEX               (0x3fUL << 11UL)
#define DEV_MMC_STATUS_DATA_STATE_MC_BUSY           (1UL << 10UL)
#define DEV_MMC_STATUS_DATA_BUSY                    (1UL << 9UL)
#define DEV_MMC_STATUS_DATA_3_STATUS                (1UL << 8UL)
#define DEV_MMC_STATUS_COMMAND_FSM_STATES_MASK      (0xfUL << 4UL)
#define DEV_MMC_STATUS_FIFO_FULL                    (1UL << 3UL)
#define DEV_MMC_STATUS_FIFO_EMPTY                   (1UL << 2UL)
#define DEV_MMC_STATUS_FIFO_TX_WATERMARK            (1UL << 1UL)
#define DEV_MMC_STATUS_FIFO_RX_WATERMARK            (1Ul << 0)


#define   DEV_MMC_BASE              _IO_((uint32_t)0x200C0000)
#define   DEV_MMC                   ((DEV_SDC_RegDef *) DEV_MMC_BASE)

uint32_t hal_mmc_init(uint32_t bus_width, uint32_t clk, MMC_Info mmc_info);

//uint32_t hal_mmc_read_data(uint8_t *buffer,uint32_t mmc_addr,uint32_t len,uint32_t dma_ch,MMC_Info mmc_info);
//
//void mmc_read_dma_init(uint32_t dma_ch);
#endif /* SRC_EMMC_H_ */
