#ifndef __AON_PMU_FIELD_H__
#define __AON_PMU_FIELD_H__

#include "sp2cw3.h"
/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************PWR_CTL***********************************/
typedef struct
{
    __IO uint32_t STATE               : 2;
    __IO uint32_t RESTART_TIME        : 2;
    __IO uint32_t PMU_SPEED           : 1;
    uint32_t RESERVED0           : 3;
    __IO uint32_t BIAS_NORM_EN        : 1;
    __IO uint32_t IOVCC_NORM_EN       : 1;
    __IO uint32_t DVDD_NORM_EN        : 1;
    __IO uint32_t VDDQ_NORM_EN        : 1;
    __IO uint32_t AVCC_NORM_EN        : 1;
    __IO uint32_t CPP_NORM_EN         : 1;
    uint32_t RESERVED1           : 2;
    __IO uint32_t BIAS_FORCE_EN       : 1;
    __IO uint32_t IOVCC_FORCE_EN      : 1;
    __IO uint32_t DVDD_FORCE_EN       : 1;
    __IO uint32_t VDDQ_FORCE_EN       : 1;
    __IO uint32_t AVCC_FORCE_EN       : 1;
    __IO uint32_t CPP_FORCE_EN        : 1;
    uint32_t RESERVED2           : 2;
    __IO uint32_t IOVCC_DET_EN        : 1;
    __IO uint32_t DVDD_DET_EN         : 1;
    __IO uint32_t AVCC_DET_EN         : 1;
    __IO uint32_t CPP_DET_EN          : 1;
    uint32_t RESERVED3           : 4;
} AON_PMU_PWR_CTL_Field;
/****AON_PMUPWR_CTL end****/

/***********************************VOL_CTL***********************************/
typedef struct
{
    __IO uint32_t SVCC_VOL            : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t SVDD_VOL            : 2;
    uint32_t RESERVED1           : 2;
    __IO uint32_t DVDD_VOL            : 3;
    uint32_t RESERVED2           : 1;
    __IO uint32_t AVCC_VOL            : 3;
    uint32_t RESERVED3           : 1;
    __IO uint32_t IOVCC_VOL           : 4;
    __IO uint32_t CPP_VOL             : 2;
    uint32_t RESERVED4           : 2;
    __IO uint32_t AVDD_VOL            : 2;
    uint32_t RESERVED5           : 6;
} AON_PMU_VOL_CTL_Field;
/****AON_PMUVOL_CTL end****/

/***********************************CLK_CTL***********************************/
typedef struct
{
    __IO uint32_t OSC_DEV_KEEP        : 1;
    __IO uint32_t OSC_XTAL_KEEP       : 1;
    __IO uint32_t PLL_CORE_KEEP       : 1;
    __IO uint32_t PLL_AUDIO_KEEP      : 1;
    uint32_t RESERVED0           : 28;
} AON_PMU_CLK_CTL_Field;
/****AON_PMUCLK_CTL end****/

/***********************************REF_TRIM***********************************/
typedef struct
{
    __IO uint32_t VREF_TRIM           : 5;
    uint32_t RESERVED0           : 3;
    __IO uint32_t IREF_TRIM           : 4;
    __IO uint32_t VBG1_TRIM           : 3;
    uint32_t RESERVED1           : 1;
    __IO uint32_t CMU_VBG2_TRIM       : 3;
    uint32_t RESERVED2           : 13;
} AON_PMU_REF_TRIM_Field;
/****AON_PMUREF_TRIM end****/

/***********************************ONOFF***********************************/
typedef struct
{
    __I  uint32_t ONOFF_IN            : 1;
    __I  uint32_t PWR_STA             : 1;
    __I  uint32_t ONOFF_DEB           : 1;
    __IO uint32_t ONOFF_BOOT          : 1;
    __IO uint32_t ONOFF_DEB_TIME      : 2;
    uint32_t RESERVED0           : 2;
    __IO uint32_t ONOFF_SHORT_TIME    : 3;
    __IO uint32_t ONOFF_ULONG_TIME    : 1;
    __IO uint32_t ONOFF_LONG_TIME     : 2;
    uint32_t RESERVED1           : 2;
    __IO uint32_t ONOFF_SPEED         : 1;
    __IO uint32_t ONOFF_SEL           : 1;
    __IO uint32_t GPIO_SEL            : 1;
    uint32_t RESERVED2           : 1;
    __IO uint32_t ONOFF_EDGE          : 3;
    uint32_t RESERVED3           : 9;
} AON_PMU_ONOFF_Field;
/****AON_PMUONOFF end****/

/***********************************PWR_STA***********************************/
typedef struct
{
    __IO uint32_t DVDDOK              : 1;
    __IO uint32_t AVCCOK              : 1;
    __IO uint32_t IOVCCOK             : 1;
    __IO uint32_t CPPOK               : 1;
    uint32_t RESERVED0           : 28;
} AON_PMU_PWR_STA_Field;
/****AON_PMUPWR_STA end****/

/***********************************IE***********************************/
typedef struct
{
    __IO uint32_t ONOFF_SHORT         : 1;
    __IO uint32_t ONOFF_LONG          : 1;
    __IO uint32_t ONOFF_ULONG         : 1;
    __IO uint32_t ONOFF_XLONG         : 1;
    __IO uint32_t ONOFF_EDGE          : 1;
    uint32_t RESERVED0           : 27;
} AON_PMU_IE_Field;
/****AON_PMUIE end****/

/***********************************PD***********************************/
typedef struct
{
    __IO uint32_t ONOFF_SHORT         : 1;
    __IO uint32_t ONOFF_LONG          : 1;
    __IO uint32_t ONOFF_ULONG         : 1;
    __IO uint32_t ONOFF_XLONG         : 1;
    __IO uint32_t ONOFF_EDGE          : 1;
    uint32_t RESERVED0           : 27;
} AON_PMU_PD_Field;
/****AON_PMUPD end****/

/***********************************WKEN***********************************/
typedef struct
{
    __IO uint32_t ONOFF_SHORT         : 1;
    __IO uint32_t ONOFF_LONG          : 1;
    __IO uint32_t ONOFF_ULONG         : 1;
    __IO uint32_t ONOFF_XLONG         : 1;
    __IO uint32_t ONOFF_EDGE          : 1;
    uint32_t RESERVED0           : 27;
} AON_PMU_WKEN_Field;
/****AON_PMUWKEN end****/

/***********************************RSTEN***********************************/
typedef struct
{
    __IO uint32_t RESET_SHORT         : 1;
    __IO uint32_t RESET_LONG          : 1;
    __IO uint32_t RESET_ULONG         : 1;
    __IO uint32_t RESET_XLONG         : 1;
    __IO uint32_t RESET_SVDD          : 1;
    uint32_t RESERVED0           : 3;
    __IO uint32_t RESTART_SHORT       : 1;
    __IO uint32_t RESTART_LONG        : 1;
    __IO uint32_t RESTART_ULONG       : 1;
    __IO uint32_t RESTART_XLONG       : 1;
    __IO uint32_t RESTART_SVDD        : 1;
    uint32_t RESERVED1           : 16;
} AON_PMU_RSTEN_Field;
/****AON_PMURSTEN end****/

/***********************************AON_PMU register***********************************/
typedef struct
{
    union
    {
        __IO    uint32_t    PWR_CTL;                                 /* 0x0    PMU Power Control */
        AON_PMU_PWR_CTL_Field    PWR_CTL_f;
    };
    union
    {
        __IO    uint32_t    VOL_CTL;                                 /* 0x4    PMU Voltage Control */
        AON_PMU_VOL_CTL_Field    VOL_CTL_f;
    };
    union
    {
        __IO    uint32_t    CLK_CTL;                                 /* 0x8    PMU Clock Control */
        AON_PMU_CLK_CTL_Field    CLK_CTL_f;
    };
    union
    {
        __IO    uint32_t    REF_TRIM;                                /* 0xc    PMU Reference Control */
        AON_PMU_REF_TRIM_Field    REF_TRIM_f;
    };
    union
    {
        __IO    uint32_t    ONOFF;                                   /* 0x10    PMU Onoff Control */
        AON_PMU_ONOFF_Field    ONOFF_f;
    };
    union
    {
        __IO    uint32_t    PWR_STA;                                 /* 0x14    PMU Status */
        AON_PMU_PWR_STA_Field    PWR_STA_f;
    };
    uint32_t    RESERVED0[2];
    union
    {
        __IO    uint32_t    IE;                                      /* 0x20    PMU Interrupt Control */
        AON_PMU_IE_Field    IE_f;
    };
    union
    {
        __IO    uint32_t    PD;                                      /* 0x24    PMU Pending */
        AON_PMU_PD_Field    PD_f;
    };
    union
    {
        __IO    uint32_t    WKEN;                                    /* 0x28    PMU Reset Control */
        AON_PMU_WKEN_Field    WKEN_f;
    };
    union
    {
        __IO    uint32_t    RSTEN;                                   /* 0x2c    PMU Wakeup */
        AON_PMU_RSTEN_Field    RSTEN_f;
    };
} AON_PMU_RegDef_f;
/****AON_PMU end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
