#ifndef __DEV_ASIN_H__
#define __DEV_ASIN_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************ASI_CFG***********************************/
#define DEV_ASIn_CFG_LSB_MODE_MSB                               (0x0UL<<30)
#define DEV_ASIn_CFG_LSB_MODE_LSB                               (0x1UL<<30)
#define DEV_ASIn_CFG_LSB_MODE_MASK                              (0x1UL<<30)
#define DEV_ASIn_CFG_RX_FIFO_THR_MASK                           (0x3fUL<<24)
#define DEV_ASIn_CFG_DSD_DAT_FMT_HIGH16BIT                      (0x0UL<<22)
#define DEV_ASIn_CFG_DSD_DAT_FMT_LOW_16BIT                      (0x1UL<<22)
#define DEV_ASIn_CFG_DSD_DAT_FMT_MIDDLE16BIT                    (0x2UL<<22)
#define DEV_ASIn_CFG_DSD_DAT_FMT_32BIT                          (0x3UL<<22)
#define DEV_ASIn_CFG_DSD_DAT_FMT_MASK                           (0x3UL<<22)
#define DEV_ASIn_CFG_TX_FIFO_THR_MASK                           (0x3fUL<<16)
#define DEV_ASIn_CFG_LOOPBACK_DISABLE                           (0x0UL<<15)
#define DEV_ASIn_CFG_LOOPBACK_ENABLE                            (0x1UL<<15)
#define DEV_ASIn_CFG_LOOPBACK_MASK                              (0x1UL<<15)
#define DEV_ASIn_CFG_DAT_FMT_HIGH16BIT                          (0x0UL<<12)
#define DEV_ASIn_CFG_DAT_FMT_LOW_16BIT                          (0x1UL<<12)
#define DEV_ASIn_CFG_DAT_FMT_HIGH24BIT                          (0x2UL<<12)
#define DEV_ASIn_CFG_DAT_FMT_LOW_24BIT                          (0x3UL<<12)
#define DEV_ASIn_CFG_DAT_FMT_MASK                               (0x3UL<<12)
#define DEV_ASIn_CFG_VLD_WIDTH_16BIT                            (0x0UL<<10)
#define DEV_ASIn_CFG_VLD_WIDTH_20BIT                            (0x1UL<<10)
#define DEV_ASIn_CFG_VLD_WIDTH_24BIT                            (0x2UL<<10)
#define DEV_ASIn_CFG_VLD_WIDTH_32BIT                            (0x3UL<<10)
#define DEV_ASIn_CFG_VLD_WIDTH_MASK                             (0x3UL<<10)
#define DEV_ASIn_CFG_DSD_CTL_DSD_CTLOFF                         (0x0UL<<9)
#define DEV_ASIn_CFG_DSD_CTL_DSD_CTLON                          (0x1UL<<9)
#define DEV_ASIn_CFG_DSD_CTL_MASK                               (0x1UL<<9)
#define DEV_ASIn_CFG_CHN_WIDTH_16BCLKCYCLE                      (0x0UL<<8)
#define DEV_ASIn_CFG_CHN_WIDTH_32BCLKCYCLE                      (0x1UL<<8)
#define DEV_ASIn_CFG_CHN_WIDTH_MASK                             (0x1UL<<8)
#define DEV_ASIn_CFG_MASTER_SLAVE_MODE                          (0x0UL<<7)
#define DEV_ASIn_CFG_MASTER_MASTERMODE                          (0x1UL<<7)
#define DEV_ASIn_CFG_MASTER_MASK                                (0x1UL<<7)
#define DEV_ASIn_CFG_CHN_NUM(_channel_number_)                  (((_channel_number_)-1)<<4)
#define DEV_ASIn_CFG_CHN_NUM_MASK                               (0x7UL<<4)
#define DEV_ASIn_CFG_FRM_FMT_0BCLK                              (0x0UL<<2)
#define DEV_ASIn_CFG_FRM_FMT_1BCLK                              (0x1UL<<2)
#define DEV_ASIn_CFG_FRM_FMT_MASK                               (0x3UL<<2)
#define DEV_ASIn_CFG_MODE_SEL_I2SMODE                           (0x0UL<<0)
#define DEV_ASIn_CFG_MODE_SEL_PCMMODE                           (0x1UL<<0)
#define DEV_ASIn_CFG_MODE_SEL_MASK                              (0x3UL<<0)
/****ASI_CFG end****/


/***********************************ASI_CTL***********************************/
#define DEV_ASIn_CTL_IO_STA_LOW_LEVEL                           (0x0UL<<16)
#define DEV_ASIn_CTL_IO_STA_HIGH_LEVEL                          (0x1UL<<16)
#define DEV_ASIn_CTL_IO_STA_MASK                                (0x3UL<<16)
#define DEV_ASIn_CTL_Slot7_en_DISABLE                           (0x0UL<<15)
#define DEV_ASIn_CTL_Slot7_en_ENABLE                            (0x1UL<<15)
#define DEV_ASIn_CTL_Slot7_en_MASK                              (0x1UL<<15)
#define DEV_ASIn_CTL_Slot6_en_DISABLE                           (0x0UL<<14)
#define DEV_ASIn_CTL_Slot6_en_ENABLE                            (0x1UL<<14)
#define DEV_ASIn_CTL_Slot6_en_MASK                              (0x1UL<<14)
#define DEV_ASIn_CTL_Slot5_en_DISABLE                           (0x0UL<<13)
#define DEV_ASIn_CTL_Slot5_en_ENABLE                            (0x1UL<<13)
#define DEV_ASIn_CTL_Slot5_en_MASK                              (0x1UL<<13)
#define DEV_ASIn_CTL_Slot4_en_DISABLE                           (0x0UL<<12)
#define DEV_ASIn_CTL_Slot4_en_ENABLE                            (0x1UL<<12)
#define DEV_ASIn_CTL_Slot4_en_MASK                              (0x1UL<<12)
#define DEV_ASIn_CTL_Slot3_en_DISABLE                           (0x0UL<<11)
#define DEV_ASIn_CTL_Slot3_en_ENABLE                            (0x1UL<<11)
#define DEV_ASIn_CTL_Slot3_en_MASK                              (0x1UL<<11)
#define DEV_ASIn_CTL_Slot2_en_DISABLE                           (0x0UL<<10)
#define DEV_ASIn_CTL_Slot2_en_ENABLE                            (0x1UL<<10)
#define DEV_ASIn_CTL_Slot2_en_MASK                              (0x1UL<<10)
#define DEV_ASIn_CTL_Slot1_en_DISABLE                           (0x0UL<<9)
#define DEV_ASIn_CTL_Slot1_en_ENABLE                            (0x1UL<<9)
#define DEV_ASIn_CTL_Slot1_en_MASK                              (0x1UL<<9)
#define DEV_ASIn_CTL_Slot0_en_DISABLE                           (0x0UL<<8)
#define DEV_ASIn_CTL_Slot0_en_ENABLE                            (0x1UL<<8)
#define DEV_ASIn_CTL_Slot0_en_MASK                              (0x1UL<<8)
#define DEV_ASIn_CTL_RX_FIFO_RST_RXFIFOWORK                     (0x0UL<<7)
#define DEV_ASIn_CTL_RX_FIFO_RST_RXFIFORESET                    (0x1UL<<7)
#define DEV_ASIn_CTL_RX_FIFO_RST_MASK                           (0x1UL<<7)
#define DEV_ASIn_CTL_TX_FIFO_RST_TXFIFOWORK                     (0x0UL<<6)
#define DEV_ASIn_CTL_TX_FIFO_RST_TXFIFORESET                    (0x1UL<<6)
#define DEV_ASIn_CTL_TX_FIFO_RST_MASK                           (0x1UL<<6)
#define DEV_ASIn_CTL_RX_SRC_SEL_AHB                             (0x0UL<<5)
#define DEV_ASIn_CTL_RX_SRC_SEL_SRC                             (0x1UL<<5)
#define DEV_ASIn_CTL_RX_SRC_SEL_MASK                            (0x1UL<<5)
#define DEV_ASIn_CTL_TX_SRC_SEL_AHB                             (0x0UL<<4)
#define DEV_ASIn_CTL_TX_SRC_SEL_SRC                             (0x1UL<<4)
#define DEV_ASIn_CTL_TX_SRC_SEL_MASK                            (0x1UL<<4)
#define DEV_ASIn_CTL_RX_DMA_EN_DISABLE                          (0x0UL<<3)
#define DEV_ASIn_CTL_RX_DMA_EN_ENABLE                           (0x1UL<<3)
#define DEV_ASIn_CTL_RX_DMA_EN_MASK                             (0x1UL<<3)
#define DEV_ASIn_CTL_TX_DMA_EN_DISABLE                          (0x0UL<<2)
#define DEV_ASIn_CTL_TX_DMA_EN_ENABLE                           (0x1UL<<2)
#define DEV_ASIn_CTL_TX_DMA_EN_MASK                             (0x1UL<<2)
#define DEV_ASIn_CTL_RX_EN_DISABLE                              (0x0UL<<1)
#define DEV_ASIn_CTL_RX_EN_ENABLE                               (0x1UL<<1)
#define DEV_ASIn_CTL_RX_EN_MASK                                 (0x1UL<<1)
#define DEV_ASIn_CTL_TX_EN_DISABLE                              (0x0UL<<0)
#define DEV_ASIn_CTL_TX_EN_ENABLE                               (0x1UL<<0)
#define DEV_ASIn_CTL_TX_EN_MASK                                 (0x1UL<<0)
/****ASI_CTL end****/


/***********************************ASI_IE***********************************/
#define DEV_ASIn_IE_RX_FIFO_UF                                  (0x1UL<<6)
#define DEV_ASIn_IE_RX_FIFO_OF                                  (0x1UL<<5)
#define DEV_ASIn_IE_RX_IRQ                                      (0x1UL<<4)
#define DEV_ASIn_IE_TX_FIFO_UF                                  (0x1UL<<2)
#define DEV_ASIn_IE_TX_FIFO_OF                                  (0x1UL<<1)
#define DEV_ASIn_IE_TX_IRQ                                      (0x1UL<<0)
/****ASI_IE end****/


/***********************************ASI_PD***********************************/
#define DEV_ASIn_PD_RX_FIFO_UF                                  (0x1UL<<6)
#define DEV_ASIn_PD_RX_FIFO_OF                                  (0x1UL<<5)
#define DEV_ASIn_PD_RX_IRQ                                      (0x1UL<<4)
#define DEV_ASIn_PD_TX_FIFO_UF                                  (0x1UL<<2)
#define DEV_ASIn_PD_TX_FIFO_OF                                  (0x1UL<<1)
#define DEV_ASIn_PD_TX_IRQ                                      (0x1UL<<0)
/****ASI_PD end****/


/***********************************ASI_STA***********************************/
#define DEV_ASIn_STA_RX_BUSY                                    (0x1UL<<28)
#define DEV_ASIn_STA_RX_FIFO_FULL                               (0x1UL<<27)
#define DEV_ASIn_STA_RX_FIFO_AFUL                               (0x1UL<<26)
#define DEV_ASIn_STA_RX_FIFO_EMPT                               (0x1UL<<25)
#define DEV_ASIn_STA_RX_FIFO_AEMP                               (0x1UL<<24)
#define DEV_ASIn_STA_RX_FIFO_RLVL_MASK                          (0x3fUL<<16)
#define DEV_ASIn_STA_TX_BUSY                                    (0x1UL<<12)
#define DEV_ASIn_STA_TX_FIFO_FULL                               (0x1UL<<11)
#define DEV_ASIn_STA_TX_FIFO_AFUL                               (0x1UL<<10)
#define DEV_ASIn_STA_TX_FIFO_EMPT                               (0x1UL<<9)
#define DEV_ASIn_STA_TX_FIFO_AEMP                               (0x1UL<<8)
#define DEV_ASIn_STA_TX_FIFO_WLVL_MASK                          (0x3fUL<<0)
/****ASI_STA end****/


/***********************************ASI_TX_CNT***********************************/
#define DEV_ASIn_TX_CNT_MASK                                    (0xffffffffUL<<0)
/****ASI_TX_CNT end****/


/***********************************ASI_RX_CNT***********************************/
#define DEV_ASIn_RX_CNT_MASK                                    (0xffffffffUL<<0)
/****ASI_RX_CNT end****/


/***********************************ASI_TX_BUF***********************************/
#define DEV_ASIn_TX_BUF_TX_DAT_MASK                             (0xffffffffUL<<0)
/****ASI_TX_BUF end****/


/***********************************ASI_RX_BUF***********************************/
#define DEV_ASIn_RX_BUF_RX_DAT_MASK                             (0xffffffffUL<<0)
/****ASI_RX_BUF end****/


/***********************************DEV_ASIn register***********************************/
typedef struct
{

    __IO    uint32_t    CFG;                                     /* 0x0    ASI Configure */
    uint32_t    RESERVED0;
    __IO    uint32_t    CTL;                                     /* 0x8    ASI Control */
    __IO    uint32_t    IE;                                      /* 0xc    ASI Interrupt Enable */
    __IO    uint32_t    PD;                                      /* 0x10    ASI Interrupt Pending */
    __I     uint32_t    STA;                                     /* 0x14    ASI Status */
    __I     uint32_t    TX_CNT;                                  /* 0x18    ASI TX Frame Counter */
    __I     uint32_t    RX_CNT;                                  /* 0x1c    ASI RX Frame Counter */
    __O     uint32_t    TX_BUF;                                  /* 0x20    ASI TX FIFO */
    __I     uint32_t    RX_BUF;                                  /* 0x24    ASI RX FIFO */
} DEV_ASIn_RegDef;
/****DEV_ASIn end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
