#ifndef __AON_CMU_H__
#define __AON_CMU_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************CMU_CLKEN0***********************************/
#define AON_CMU_CLKEN0_CLKSEL_AON_OSC_PMU                       (0x0UL<<9)
#define AON_CMU_CLKEN0_CLKSEL_AON_BUS_CLK                       (0x1UL<<9)
#define AON_CMU_CLKEN0_CLKSEL_AON_MASK                          (0x1UL<<9)
#define AON_CMU_CLKEN0_CLKMOD_AON_HARDWARE                      (0x0UL<<8)
#define AON_CMU_CLKEN0_CLKMOD_AON_SOFTWARE                      (0x1UL<<8)
#define AON_CMU_CLKEN0_CLKMOD_AON_MASK                          (0x1UL<<8)
#define AON_CMU_CLKEN0_DEB                                      (0x1UL<<3)
#define AON_CMU_CLKEN0_BUFF                                     (0x1UL<<2)
#define AON_CMU_CLKEN0_AUDI                                     (0x1UL<<1)
#define AON_CMU_CLKEN0_LRADC                                    (0x1UL<<0)
/****CMU_CLKEN0 end****/


/***********************************CMU_LRADCCLK***********************************/
#define AON_CMU_LRADCCLK_DIV_MASK                               (0xffUL<<4)
#define AON_CMU_LRADCCLK_SEL_OSC_ADC                            (0x0UL<<0)
#define AON_CMU_LRADCCLK_SEL_OSC_DEV                            (0x1UL<<0)
#define AON_CMU_LRADCCLK_SEL_OSC_XTAL                           (0x2UL<<0)
#define AON_CMU_LRADCCLK_SEL_EXT_CLK                            (0x3UL<<0)
#define AON_CMU_LRADCCLK_SEL_MASK                               (0x3UL<<0)
/****CMU_LRADCCLK end****/


/***********************************CMU_DMICCLK***********************************/
#define AON_CMU_DMICCLK_DIV_MASK                                (0xffUL<<4)
#define AON_CMU_DMICCLK_SEL_OSC_ADC                             (0x0UL<<0)
#define AON_CMU_DMICCLK_SEL_OSC_DEV                             (0x1UL<<0)
#define AON_CMU_DMICCLK_SEL_OSC_XTAL                            (0x2UL<<0)
#define AON_CMU_DMICCLK_SEL_EXT_CLK                             (0x3UL<<0)
#define AON_CMU_DMICCLK_SEL_MASK                                (0x3UL<<0)
/****CMU_DMICCLK end****/


/***********************************CMU_I2SRXCLK***********************************/
#define AON_CMU_I2SRXCLK_DIV_MASK                               (0xffUL<<4)
#define AON_CMU_I2SRXCLK_SEL_OSC_ADC                            (0x0UL<<0)
#define AON_CMU_I2SRXCLK_SEL_OSC_DEV                            (0x1UL<<0)
#define AON_CMU_I2SRXCLK_SEL_OSC_XTAL                           (0x2UL<<0)
#define AON_CMU_I2SRXCLK_SEL_EXT_CLK                            (0x3UL<<0)
#define AON_CMU_I2SRXCLK_SEL_MASK                               (0x3UL<<0)
/****CMU_I2SRXCLK end****/


/***********************************CMU_CMUDBG***********************************/
#define AON_CMU_CMUDBG_DIV_1                                    (0x0UL<<8)
#define AON_CMU_CMUDBG_DIV_2                                    (0x1UL<<8)
#define AON_CMU_CMUDBG_DIV_4                                    (0x2UL<<8)
#define AON_CMU_CMUDBG_DIV_8                                    (0x3UL<<8)
#define AON_CMU_CMUDBG_DIV_16                                   (0x4UL<<8)
#define AON_CMU_CMUDBG_DIV_32                                   (0x5UL<<8)
#define AON_CMU_CMUDBG_DIV_64                                   (0x6UL<<8)
#define AON_CMU_CMUDBG_DIV_128                                  (0x7UL<<8)
#define AON_CMU_CMUDBG_DIV_MASK                                 (0x7UL<<8)
#define AON_CMU_CMUDBG_SEL_0                                    (0x0UL<<0)
#define AON_CMU_CMUDBG_SEL_OSC_ADC                              (0x1UL<<0)
#define AON_CMU_CMUDBG_SEL_OSC_DEV                              (0x2UL<<0)
#define AON_CMU_CMUDBG_SEL_OSC_XTAL                             (0x3UL<<0)
#define AON_CMU_CMUDBG_SEL_EXT_CLK                              (0x4UL<<0)
#define AON_CMU_CMUDBG_SEL_AHB_CLK                              (0x5UL<<0)
#define AON_CMU_CMUDBG_SEL_LRADC_CLK                            (0x7UL<<0)
#define AON_CMU_CMUDBG_SEL_DMIC_CLK                             (0x8UL<<0)
#define AON_CMU_CMUDBG_SEL_I2SRX_CLK                            (0x9UL<<0)
#define AON_CMU_CMUDBG_SEL_DEB_CLK                              (0xaUL<<0)
#define AON_CMU_CMUDBG_SEL_PMU_CLK                              (0xbUL<<0)
#define AON_CMU_CMUDBG_SEL_RMU_CLK                              (0xcUL<<0)
#define AON_CMU_CMUDBG_SEL_LRADC_HCLK                           (0xdUL<<0)
#define AON_CMU_CMUDBG_SEL_AUDI_HCLK                            (0xeUL<<0)
#define AON_CMU_CMUDBG_SEL_MEMC_CLK                             (0xfUL<<0)
#define AON_CMU_CMUDBG_SEL_AON_CLK                              (0x10UL<<0)
#define AON_CMU_CMUDBG_SEL_MASK                                 (0x3fUL<<0)
/****CMU_CMUDBG end****/


/***********************************AON_CMU register***********************************/
typedef struct
{

    __IO    uint32_t    CLKEN0;                                  /* 0x0    Clock Enable */
    uint32_t    RESERVED0[3];
    __IO    uint32_t    LRADCCLK;                                /* 0x10    LRADC Clock Control */
    __IO    uint32_t    DMICCLK;                                 /* 0x14    DMIC Clock Control */
    __IO    uint32_t    I2SRXCLK;                                /* 0x18    I2SRX Clock Control */
    uint32_t    RESERVED1[55];
    __IO    uint32_t    CMUDBG;                                  /* 0xf8    Clock Debug Output */
} AON_CMU_RegDef;
/****AON_CMU end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
