#ifndef __AON_LRADC_FIELD_H__
#define __AON_LRADC_FIELD_H__

#include "sp2cw3.h"
/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************CFGn***********************************/
typedef struct
{
    __IO uint32_t EN                  : 1;
    __IO uint32_t MODE                : 1;
    __IO uint32_t SR                  : 2;
    __IO uint32_t AVG                 : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t SVK_LVL             : 10;
    __IO uint32_t SVK_EN              : 1;
    __IO uint32_t SVK_TYPE            : 1;
    __IO uint32_t SVK_EDGE            : 3;
    uint32_t RESERVED1           : 1;
    uint32_t RESERVED2           : 8;
} AON_LRADC_CFGn_Field;
/****AON_LRADCCFGn end****/

/***********************************ANA***********************************/
typedef struct
{
    __IO uint32_t LRADC_EN            : 1;
    __IO uint32_t LPCMP_EN            : 1;
    __IO uint32_t LPCMP_VOL           : 1;
    uint32_t RESERVED0           : 1;
    __IO uint32_t LRADC_PGA           : 3;
    __IO uint32_t LRADC_MIC           : 1;
    __IO uint32_t LRADC_VREF_SEL      : 1;
    uint32_t RESERVED1           : 23;
} AON_LRADC_ANA_Field;
/****AON_LRADCANA end****/

/***********************************MKV0***********************************/
typedef struct
{
    __IO uint32_t KEY_EN              : 1;
    __IO uint32_t DEB_EN              : 1;
    __IO uint32_t DEB_TIME            : 2;
    __IO uint32_t KEY_SRC             : 4;
    uint32_t RESERVED0           : 2;
    __IO uint32_t KEY_THD0            : 10;
    __IO uint32_t KEY_THD1            : 10;
    uint32_t RESERVED1           : 2;
} AON_LRADC_MKV0_Field;
/****AON_LRADCMKV0 end****/

/***********************************MKV1***********************************/
typedef struct
{
    __IO uint32_t KEY_THD2            : 10;
    __IO uint32_t KEY_THD3            : 10;
    __IO uint32_t KEY_THD4            : 10;
    uint32_t RESERVED0           : 2;
} AON_LRADC_MKV1_Field;
/****AON_LRADCMKV1 end****/

/***********************************MKV2***********************************/
typedef struct
{
    __IO uint32_t MVK0_EDGE           : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t MVK1_EDGE           : 3;
    uint32_t RESERVED1           : 1;
    __IO uint32_t MVK2_EDGE           : 3;
    uint32_t RESERVED2           : 1;
    __IO uint32_t MVK3_EDGE           : 3;
    uint32_t RESERVED3           : 1;
    __IO uint32_t MVK4_EDGE           : 3;
    uint32_t RESERVED4           : 1;
    __IO uint32_t MVK5_EDGE           : 3;
    uint32_t RESERVED5           : 9;
} AON_LRADC_MKV2_Field;
/****AON_LRADCMKV2 end****/

/***********************************CTL***********************************/
typedef struct
{
    __IO uint32_t EN                  : 1;
    __IO uint32_t LRADC_NUM           : 3;
    __IO uint32_t FRADC_CHN           : 4;
    __IO uint32_t LRADC_SELM          : 1;
    uint32_t RESERVED0           : 23;
} AON_LRADC_CTL_Field;
/****AON_LRADCCTL end****/

/***********************************IE***********************************/
typedef struct
{
    __IO uint32_t LRADC00_END_IE      : 1;
    __IO uint32_t LRADC01_END_IE      : 1;
    __IO uint32_t LRADC02_END_IE      : 1;
    __IO uint32_t LRADC03_END_IE      : 1;
    __IO uint32_t LRADC04_END_IE      : 1;
    __IO uint32_t LRADC05_END_IE      : 1;
    __IO uint32_t LRADC06_END_IE      : 1;
    __IO uint32_t LRADC07_END_IE      : 1;
    __IO uint32_t LRADC08_END_IE      : 1;
    __IO uint32_t LRADC09_END_IE      : 1;
    __IO uint32_t LRADC10_END_IE      : 1;
    __IO uint32_t LRADC11_END_IE      : 1;
    __IO uint32_t LRADC00_SVK_IE      : 1;
    __IO uint32_t LRADC01_SVK_IE      : 1;
    __IO uint32_t LRADC02_SVK_IE      : 1;
    __IO uint32_t LRADC03_SVK_IE      : 1;
    __IO uint32_t LRADC04_SVK_IE      : 1;
    __IO uint32_t LRADC05_SVK_IE      : 1;
    __IO uint32_t LRADC06_SVK_IE      : 1;
    __IO uint32_t LRADC07_SVK_IE      : 1;
    __IO uint32_t LRADC08_SVK_IE      : 1;
    __IO uint32_t LRADC09_SVK_IE      : 1;
    __IO uint32_t LRADC10_SVK_IE      : 1;
    __IO uint32_t LRADC11_SVK_IE      : 1;
    __IO uint32_t LRADC_MVK0_IE       : 1;
    __IO uint32_t LRADC_MVK1_IE       : 1;
    __IO uint32_t LRADC_MVK2_IE       : 1;
    __IO uint32_t LRADC_MVK3_IE       : 1;
    __IO uint32_t LRADC_MVK4_IE       : 1;
    __IO uint32_t LRADC_MVK5_IE       : 1;
    uint32_t RESERVED0           : 2;
} AON_LRADC_IE_Field;
/****AON_LRADCIE end****/

/***********************************WKEN***********************************/
typedef struct
{
    __IO uint32_t LRADC00_END_WKEN    : 1;
    __IO uint32_t LRADC01_END_WKEN    : 1;
    __IO uint32_t LRADC02_END_WKEN    : 1;
    __IO uint32_t LRADC03_END_WKEN    : 1;
    __IO uint32_t LRADC04_END_WKEN    : 1;
    __IO uint32_t LRADC05_END_WKEN    : 1;
    __IO uint32_t LRADC06_END_WKEN    : 1;
    __IO uint32_t LRADC07_END_WKEN    : 1;
    __IO uint32_t LRADC08_END_WKEN    : 1;
    __IO uint32_t LRADC09_END_WKEN    : 1;
    __IO uint32_t LRADC10_END_WKEN    : 1;
    __IO uint32_t LRADC11_END_WKEN    : 1;
    __IO uint32_t LRADC00_SVK_WKEN    : 1;
    __IO uint32_t LRADC01_SVK_WKEN    : 1;
    __IO uint32_t LRADC02_SVK_WKEN    : 1;
    __IO uint32_t LRADC03_SVK_WKEN    : 1;
    __IO uint32_t LRADC04_SVK_WKEN    : 1;
    __IO uint32_t LRADC05_SVK_WKEN    : 1;
    __IO uint32_t LRADC06_SVK_WKEN    : 1;
    __IO uint32_t LRADC07_SVK_WKEN    : 1;
    __IO uint32_t LRADC08_SVK_WKEN    : 1;
    __IO uint32_t LRADC09_SVK_WKEN    : 1;
    __IO uint32_t LRADC10_SVK_WKEN    : 1;
    __IO uint32_t LRADC11_SVK_WKEN    : 1;
    __IO uint32_t LRADC_MVK0_WKEN     : 1;
    __IO uint32_t LRADC_MVK1_WKEN     : 1;
    __IO uint32_t LRADC_MVK2_WKEN     : 1;
    __IO uint32_t LRADC_MVK3_WKEN     : 1;
    __IO uint32_t LRADC_MVK4_WKEN     : 1;
    __IO uint32_t LRADC_MVK5_WKEN     : 1;
    uint32_t RESERVED0           : 2;
} AON_LRADC_WKEN_Field;
/****AON_LRADCWKEN end****/

/***********************************PD***********************************/
typedef struct
{
    __IO uint32_t LRADC00_END_PD      : 1;
    __IO uint32_t LRADC01_END_PD      : 1;
    __IO uint32_t LRADC02_END_PD      : 1;
    __IO uint32_t LRADC03_END_PD      : 1;
    __IO uint32_t LRADC04_END_PD      : 1;
    __IO uint32_t LRADC05_END_PD      : 1;
    __IO uint32_t LRADC06_END_PD      : 1;
    __IO uint32_t LRADC07_END_PD      : 1;
    __IO uint32_t LRADC08_END_PD      : 1;
    __IO uint32_t LRADC09_END_PD      : 1;
    __IO uint32_t LRADC10_END_PD      : 1;
    __IO uint32_t LRADC11_END_PD      : 1;
    __IO uint32_t LRADC00_SVK_PD      : 1;
    __IO uint32_t LRADC01_SVK_PD      : 1;
    __IO uint32_t LRADC02_SVK_PD      : 1;
    __IO uint32_t LRADC03_SVK_PD      : 1;
    __IO uint32_t LRADC04_SVK_PD      : 1;
    __IO uint32_t LRADC05_SVK_PD      : 1;
    __IO uint32_t LRADC06_SVK_PD      : 1;
    __IO uint32_t LRADC07_SVK_PD      : 1;
    __IO uint32_t LRADC08_SVK_PD      : 1;
    __IO uint32_t LRADC09_SVK_PD      : 1;
    __IO uint32_t LRADC10_SVK_PD      : 1;
    __IO uint32_t LRADC11_SVK_PD      : 1;
    __IO uint32_t LRADC_MVK0_PD       : 1;
    __IO uint32_t LRADC_MVK1_PD       : 1;
    __IO uint32_t LRADC_MVK2_PD       : 1;
    __IO uint32_t LRADC_MVK3_PD       : 1;
    __IO uint32_t LRADC_MVK4_PD       : 1;
    __IO uint32_t LRADC_MVK5_PD       : 1;
    uint32_t RESERVED0           : 2;
} AON_LRADC_PD_Field;
/****AON_LRADCPD end****/

/***********************************DATn***********************************/
typedef struct
{
    __IO uint32_t DATA                : 10;
    uint32_t RESERVED0           : 22;
} AON_LRADC_DATn_Field;
/****AON_LRADCDATn end****/

/***********************************KEYD***********************************/
typedef struct
{
    __I  uint32_t LRADC00_SVK         : 1;
    __I  uint32_t LRADC01_SVK         : 1;
    __I  uint32_t LRADC02_SVK         : 1;
    __I  uint32_t LRADC03_SVK         : 1;
    __I  uint32_t LRADC04_SVK         : 1;
    __I  uint32_t LRADC05_SVK         : 1;
    __I  uint32_t LRADC06_SVK         : 1;
    __I  uint32_t LRADC07_SVK         : 1;
    __I  uint32_t LRADC08_SVK         : 1;
    __I  uint32_t LRADC09_SVK         : 1;
    __I  uint32_t LRADC10_SVK         : 1;
    __I  uint32_t LRADC11_SVK         : 1;
    __I  uint32_t LRADC_MVK0          : 1;
    __I  uint32_t LRADC_MVK1          : 1;
    __I  uint32_t LRADC_MVK2          : 1;
    __I  uint32_t LRADC_MVK3          : 1;
    __I  uint32_t LRADC_MVK4          : 1;
    __I  uint32_t LRADC_MVK5          : 1;
    uint32_t RESERVED0           : 14;
} AON_LRADC_KEYD_Field;
/****AON_LRADCKEYD end****/

/***********************************AON_LRADC register***********************************/
typedef struct
{
    union
    {
        __IO    uint32_t    CFGn[12];                                /* 0x0    LRADC Channel 00 Configuration */
        AON_LRADC_CFGn_Field    CFGn_f[12];
    };
    union
    {
        __IO    uint32_t    ANA;                                     /* 0x30    LRADC Analog Control */
        AON_LRADC_ANA_Field    ANA_f;
    };
    union
    {
        __IO    uint32_t    MKV0;                                    /* 0x34    LRADC Key Control0 */
        AON_LRADC_MKV0_Field    MKV0_f;
    };
    union
    {
        __IO    uint32_t    MKV1;                                    /* 0x38    LRADC Key Control1 */
        AON_LRADC_MKV1_Field    MKV1_f;
    };
    union
    {
        __IO    uint32_t    MKV2;                                    /* 0x3c    LRADC Key Control2 */
        AON_LRADC_MKV2_Field    MKV2_f;
    };
    union
    {
        __IO    uint32_t    CTL;                                     /* 0x40    LRADC Control */
        AON_LRADC_CTL_Field    CTL_f;
    };
    union
    {
        __IO    uint32_t    IE;                                      /* 0x44    LRADC Interrupt Enable */
        AON_LRADC_IE_Field    IE_f;
    };
    union
    {
        __IO    uint32_t    WKEN;                                    /* 0x48    LRADC Wakeup Enable */
        AON_LRADC_WKEN_Field    WKEN_f;
    };
    union
    {
        __IO    uint32_t    PD;                                      /* 0x4c    LRADC Interrupt Pending */
        AON_LRADC_PD_Field    PD_f;
    };
    union
    {
        __IO    uint32_t    DATn[12];                                /* 0x50    LRADC Channel 00 Out */
        AON_LRADC_DATn_Field    DATn_f[12];
    };
    union
    {
        __I     uint32_t    KEYD;                                    /* 0x80    LRADC Key Data */
        AON_LRADC_KEYD_Field    KEYD_f;
    };
} AON_LRADC_RegDef_f;
/****AON_LRADC end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
