#ifndef __DEV_UDSP_H__
#define __DEV_UDSP_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************uDSP_CHNn_SLA***********************************/
#define DEV_UDSP_CHNn_SLA_SRC_LOWER_ADDR_MASK                   (0xffffffffUL<<0)
/****uDSP_CHNn_SLA end****/


/***********************************uDSP_CHNn_SUA***********************************/
#define DEV_UDSP_CHNn_SUA_SRC_UPPER_ADDR_MASK                   (0xffffffffUL<<0)
/****uDSP_CHNn_SUA end****/


/***********************************uDSP_CHNn_SCA***********************************/
#define DEV_UDSP_CHNn_SCA_SRC_CURRENT_ADDR_MASK                 (0xffffffffUL<<0)
/****uDSP_CHNn_SCA end****/


/***********************************uDSP_CHNn_SMF***********************************/
#define DEV_UDSP_CHNn_SMF_SRC_OFFSET_ADDR_MASK                  (0xffffUL<<16)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_TYPE_REALINT32               (0x0UL<<15)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_TYPE_COMPLEXORLONG64         (0x1UL<<15)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_TYPE_MASK                    (0x1UL<<15)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_FORMAT_LOW_24BIT             (0x0UL<<14)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_FORMAT_HIGH24BIT             (0x1UL<<14)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_FORMAT_MASK                  (0x1UL<<14)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_WIDTH_08BIT                  (0x0UL<<12)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_WIDTH_16BIT                  (0x1UL<<12)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_WIDTH_24BIT                  (0x2UL<<12)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_WIDTH_32BIT                  (0x3UL<<12)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_WIDTH_MASK                   (0x3UL<<12)
#define DEV_UDSP_CHNn_SMF_SRC_DATA_LENGTH_MASK                  (0xfffUL<<0)
/****uDSP_CHNn_SMF end****/


/***********************************uDSP_CHNn_DLA***********************************/
#define DEV_UDSP_CHNn_DLA_DST_LOWER_ADDR_MASK                   (0xffffffffUL<<0)
/****uDSP_CHNn_DLA end****/


/***********************************uDSP_CHNn_DUA***********************************/
#define DEV_UDSP_CHNn_DUA_DST_UPPER_ADDR_MASK                   (0xffffffffUL<<0)
/****uDSP_CHNn_DUA end****/


/***********************************uDSP_CHNn_DCA***********************************/
#define DEV_UDSP_CHNn_DCA_DST_CURRENT_ADDR_MASK                 (0xffffffffUL<<0)
/****uDSP_CHNn_DCA end****/


/***********************************uDSP_CHNn_DMF***********************************/
#define DEV_UDSP_CHNn_DMF_DST_OFFSET_ADDR_MASK                  (0xffffUL<<16)
#define DEV_UDSP_CHNn_DMF_DST_DATA_TYPE_REALINT32               (0x0UL<<15)
#define DEV_UDSP_CHNn_DMF_DST_DATA_TYPE_COMPLEXORLONG64         (0x1UL<<15)
#define DEV_UDSP_CHNn_DMF_DST_DATA_TYPE_MASK                    (0x1UL<<15)
#define DEV_UDSP_CHNn_DMF_DST_DATA_WIDTH_08BIT                  (0x0UL<<12)
#define DEV_UDSP_CHNn_DMF_DST_DATA_WIDTH_16BIT                  (0x1UL<<12)
#define DEV_UDSP_CHNn_DMF_DST_DATA_WIDTH_24BIT                  (0x2UL<<12)
#define DEV_UDSP_CHNn_DMF_DST_DATA_WIDTH_32BIT                  (0x3UL<<12)
#define DEV_UDSP_CHNn_DMF_DST_DATA_WIDTH_MASK                   (0x3UL<<12)
#define DEV_UDSP_CHNn_DMF_DST_DATA_LENGTH_MASK                  (0xfffUL<<0)
/****uDSP_CHNn_DMF end****/


/***********************************uDSP_CHNn_LMF0***********************************/
#define DEV_UDSP_CHNn_LMF0_FIR_BUF1_WSA_MASK                    (0xfUL<<28)
#define DEV_UDSP_CHNn_LMF0_SMA_BUF1_RSA_MASK                    (0xfUL<<24)
#define DEV_UDSP_CHNn_LMF0_SMA_BUF1_WSA_MASK                    (0xfUL<<20)
#define DEV_UDSP_CHNn_LMF0_SMA_RD_BUF1_SEL_DISABLE              (0x0UL<<17)
#define DEV_UDSP_CHNn_LMF0_SMA_RD_BUF1_SEL_ENABLE               (0x1UL<<17)
#define DEV_UDSP_CHNn_LMF0_SMA_RD_BUF1_SEL_MASK                 (0x1UL<<17)
#define DEV_UDSP_CHNn_LMF0_SMA_WR_BUF1_SEL_DISABLE              (0x0UL<<16)
#define DEV_UDSP_CHNn_LMF0_SMA_WR_BUF1_SEL_ENABLE               (0x1UL<<16)
#define DEV_UDSP_CHNn_LMF0_SMA_WR_BUF1_SEL_MASK                 (0x1UL<<16)
#define DEV_UDSP_CHNn_LMF0_SMA_BUF0_RSA_MASK                    (0xfUL<<8)
#define DEV_UDSP_CHNn_LMF0_SMA_BUF0_WSA_MASK                    (0xfUL<<4)
#define DEV_UDSP_CHNn_LMF0_SMA_RD_BUF0_SEL_DISABLE              (0x0UL<<1)
#define DEV_UDSP_CHNn_LMF0_SMA_RD_BUF0_SEL_ENABLE               (0x1UL<<1)
#define DEV_UDSP_CHNn_LMF0_SMA_RD_BUF0_SEL_MASK                 (0x1UL<<1)
#define DEV_UDSP_CHNn_LMF0_SMA_WR_BUF0_SEL_DISABLE              (0x0UL<<0)
#define DEV_UDSP_CHNn_LMF0_SMA_WR_BUF0_SEL_ENABLE               (0x1UL<<0)
#define DEV_UDSP_CHNn_LMF0_SMA_WR_BUF0_SEL_MASK                 (0x1UL<<0)
/****uDSP_CHNn_LMF0 end****/


/***********************************uDSP_CHNn_LMF1***********************************/
#define DEV_UDSP_CHNn_LMF1_FIR_BUF0_RSA_MASK                    (0x3UL<<30)
#define DEV_UDSP_CHNn_LMF1_FIR_BUF0_WSA_MASK                    (0x3UL<<28)
#define DEV_UDSP_CHNn_LMF1_MAC_BUF0_RSA_MASK                    (0xfUL<<24)
#define DEV_UDSP_CHNn_LMF1_MAC_BUF0_WSA_MASK                    (0xfUL<<20)
#define DEV_UDSP_CHNn_LMF1_LOG_BUF0_RSA_MASK                    (0x3UL<<18)
#define DEV_UDSP_CHNn_LMF1_LOG_BUF0_WSA_MASK                    (0x3UL<<16)
#define DEV_UDSP_CHNn_LMF1_FBK_BUF0_RSA_MASK                    (0x3UL<<14)
#define DEV_UDSP_CHNn_LMF1_FBK_BUF0_WSA_MASK                    (0x3UL<<12)
#define DEV_UDSP_CHNn_LMF1_SQRT_BUF0_RSA_MASK                   (0x3UL<<10)
#define DEV_UDSP_CHNn_LMF1_SQRT_BUF0_WSA_MASK                   (0x3UL<<8)
#define DEV_UDSP_CHNn_LMF1_ABS2_BUF0_RSA_MASK                   (0x3UL<<6)
#define DEV_UDSP_CHNn_LMF1_ABS2_BUF0_WSA_MASK                   (0x3UL<<4)
#define DEV_UDSP_CHNn_LMF1_ATAN_BUF0_RSA_MASK                   (0x3UL<<2)
#define DEV_UDSP_CHNn_LMF1_ATAN_BUF0_WSA_MASK                   (0x3UL<<0)
/****uDSP_CHNn_LMF1 end****/


/***********************************uDSP_CHNn_LMF2***********************************/
#define DEV_UDSP_CHNn_LMF2_SQRT_BUF1_RSA_MASK                   (0xffUL<<24)
#define DEV_UDSP_CHNn_LMF2_MUL_BUF1_RSA_MASK                    (0xffUL<<16)
#define DEV_UDSP_CHNn_LMF2_COS_BUF1_RSA_MASK                    (0xffUL<<8)
#define DEV_UDSP_CHNn_LMF2_WIN_BUF1_RSA_MASK                    (0xffUL<<0)
/****uDSP_CHNn_LMF2 end****/


/***********************************uDSP_CHNn_LMF3***********************************/
#define DEV_UDSP_CHNn_LMF3_DIV_BUF1_RSA_MASK                    (0xffUL<<24)
#define DEV_UDSP_CHNn_LMF3_FIR_BUF1_RSA_MASK                    (0xffUL<<16)
#define DEV_UDSP_CHNn_LMF3_MAC_BUF1_RSA_MASK                    (0xffUL<<8)
#define DEV_UDSP_CHNn_LMF3_FBK_BUF1_RSA_MASK                    (0xffUL<<0)
/****uDSP_CHNn_LMF3 end****/


/***********************************uDSP_CHNn_LMF4***********************************/
#define DEV_UDSP_CHNn_LMF4_DIV_SHIFT_SEL_MASK                   (0xfUL<<28)
#define DEV_UDSP_CHNn_LMF4_FIR_SHIFT_SEL_MASK                   (0xfUL<<24)
#define DEV_UDSP_CHNn_LMF4_MAC_SHIFT_SEL_MASK                   (0xfUL<<20)
#define DEV_UDSP_CHNn_LMF4_SQRT_SHIFT_SEL_MASK                  (0xfUL<<16)
#define DEV_UDSP_CHNn_LMF4_IFFT_SHIFT_SEL_MASK                  (0xfUL<<12)
#define DEV_UDSP_CHNn_LMF4_MUL_SHIFT_SEL_MASK                   (0xfUL<<8)
#define DEV_UDSP_CHNn_LMF4_FFT_SHIFT_SEL_MASK                   (0xfUL<<4)
#define DEV_UDSP_CHNn_LMF4_COS_SHIFT_SEL_MASK                   (0xfUL<<0)
/****uDSP_CHNn_LMF4 end****/


/***********************************uDSP_CHNn_CFG0***********************************/
#define DEV_UDSP_CHNn_CFG0_BUF_SWAP_BUF0STOREDATA_AND_BUF1STORECOE  (0x0UL<<25)
#define DEV_UDSP_CHNn_CFG0_BUF_SWAP_BUF1STOREDATA_AND_BUF0STORECOE  (0x1UL<<25)
#define DEV_UDSP_CHNn_CFG0_BUF_SWAP_MASK                        (0x1UL<<25)
#define DEV_UDSP_CHNn_CFG0_LOG_8BIT_DISABLE                     (0x0UL<<24)
#define DEV_UDSP_CHNn_CFG0_LOG_8BIT_ENABLE                      (0x1UL<<24)
#define DEV_UDSP_CHNn_CFG0_LOG_8BIT_MASK                        (0x1UL<<24)
#define DEV_UDSP_CHNn_CFG0_LOG_CAL_DISABLE                      (0x0UL<<23)
#define DEV_UDSP_CHNn_CFG0_LOG_CAL_ENABLE                       (0x1UL<<23)
#define DEV_UDSP_CHNn_CFG0_LOG_CAL_MASK                         (0x1UL<<23)
#define DEV_UDSP_CHNn_CFG0_FFT_POINT_0032POINT                  (0x0UL<<20)
#define DEV_UDSP_CHNn_CFG0_FFT_POINT_0064POINT                  (0x1UL<<20)
#define DEV_UDSP_CHNn_CFG0_FFT_POINT_0128POINT                  (0x2UL<<20)
#define DEV_UDSP_CHNn_CFG0_FFT_POINT_0256POINT                  (0x3UL<<20)
#define DEV_UDSP_CHNn_CFG0_FFT_POINT_0512POINT                  (0x4UL<<20)
#define DEV_UDSP_CHNn_CFG0_FFT_POINT_1024POINT                  (0x5UL<<20)
#define DEV_UDSP_CHNn_CFG0_FFT_POINT_MASK                       (0x7UL<<20)
#define DEV_UDSP_CHNn_CFG0_SMW_DISABLE                          (0x0UL<<15)
#define DEV_UDSP_CHNn_CFG0_SMW_ENABLE                           (0x1UL<<15)
#define DEV_UDSP_CHNn_CFG0_SMW_MASK                             (0x1UL<<15)
#define DEV_UDSP_CHNn_CFG0_DIV_DISABLE                          (0x0UL<<14)
#define DEV_UDSP_CHNn_CFG0_DIV_ENABLE                           (0x1UL<<14)
#define DEV_UDSP_CHNn_CFG0_DIV_MASK                             (0x1UL<<14)
#define DEV_UDSP_CHNn_CFG0_FIR_DISABLE                          (0x0UL<<13)
#define DEV_UDSP_CHNn_CFG0_FIR_ENABLE                           (0x1UL<<13)
#define DEV_UDSP_CHNn_CFG0_FIR_MASK                             (0x1UL<<13)
#define DEV_UDSP_CHNn_CFG0_MAC_DISABLE                          (0x0UL<<12)
#define DEV_UDSP_CHNn_CFG0_MAC_ENABLE                           (0x1UL<<12)
#define DEV_UDSP_CHNn_CFG0_MAC_MASK                             (0x1UL<<12)
#define DEV_UDSP_CHNn_CFG0_LOG_DISABLE                          (0x0UL<<11)
#define DEV_UDSP_CHNn_CFG0_LOG_ENABLE                           (0x1UL<<11)
#define DEV_UDSP_CHNn_CFG0_LOG_MASK                             (0x1UL<<11)
#define DEV_UDSP_CHNn_CFG0_FBK_DISABLE                          (0x0UL<<10)
#define DEV_UDSP_CHNn_CFG0_FBK_ENABLE                           (0x1UL<<10)
#define DEV_UDSP_CHNn_CFG0_FBK_MASK                             (0x1UL<<10)
#define DEV_UDSP_CHNn_CFG0_SQRT_DISABLE                         (0x0UL<<9)
#define DEV_UDSP_CHNn_CFG0_SQRT_ENABLE                          (0x1UL<<9)
#define DEV_UDSP_CHNn_CFG0_SQRT_MASK                            (0x1UL<<9)
#define DEV_UDSP_CHNn_CFG0_ABS2_DISABLE                         (0x0UL<<8)
#define DEV_UDSP_CHNn_CFG0_ABS2_ENABLE                          (0x1UL<<8)
#define DEV_UDSP_CHNn_CFG0_ABS2_MASK                            (0x1UL<<8)
#define DEV_UDSP_CHNn_CFG0_ATAN_DISABLE                         (0x0UL<<7)
#define DEV_UDSP_CHNn_CFG0_ATAN_ENABLE                          (0x1UL<<7)
#define DEV_UDSP_CHNn_CFG0_ATAN_MASK                            (0x1UL<<7)
#define DEV_UDSP_CHNn_CFG0_IFFT_DISABLE                         (0x0UL<<6)
#define DEV_UDSP_CHNn_CFG0_IFFT_ENABLE                          (0x1UL<<6)
#define DEV_UDSP_CHNn_CFG0_IFFT_MASK                            (0x1UL<<6)
#define DEV_UDSP_CHNn_CFG0_MUL_DISABLE                          (0x0UL<<5)
#define DEV_UDSP_CHNn_CFG0_MUL_ENABLE                           (0x1UL<<5)
#define DEV_UDSP_CHNn_CFG0_MUL_MASK                             (0x1UL<<5)
#define DEV_UDSP_CHNn_CFG0_FFT_DISABLE                          (0x0UL<<4)
#define DEV_UDSP_CHNn_CFG0_FFT_ENABLE                           (0x1UL<<4)
#define DEV_UDSP_CHNn_CFG0_FFT_MASK                             (0x1UL<<4)
#define DEV_UDSP_CHNn_CFG0_COS_DISABLE                          (0x0UL<<3)
#define DEV_UDSP_CHNn_CFG0_COS_ENABLE                           (0x1UL<<3)
#define DEV_UDSP_CHNn_CFG0_COS_MASK                             (0x1UL<<3)
#define DEV_UDSP_CHNn_CFG0_WIN_DISABLE                          (0x0UL<<2)
#define DEV_UDSP_CHNn_CFG0_WIN_ENABLE                           (0x1UL<<2)
#define DEV_UDSP_CHNn_CFG0_WIN_MASK                             (0x1UL<<2)
#define DEV_UDSP_CHNn_CFG0_PRE_DISABLE                          (0x0UL<<1)
#define DEV_UDSP_CHNn_CFG0_PRE_ENABLE                           (0x1UL<<1)
#define DEV_UDSP_CHNn_CFG0_PRE_MASK                             (0x1UL<<1)
#define DEV_UDSP_CHNn_CFG0_SMR_DISABLE                          (0x0UL<<0)
#define DEV_UDSP_CHNn_CFG0_SMR_ENABLE                           (0x1UL<<0)
#define DEV_UDSP_CHNn_CFG0_SMR_MASK                             (0x1UL<<0)
/****uDSP_CHNn_CFG0 end****/


/***********************************uDSP_CHNn_CFG1***********************************/
#define DEV_UDSP_CHNn_CFG1_MFCC_NUM(_total_)                    (((_total_)-1)<<16)
#define DEV_UDSP_CHNn_CFG1_MFCC_NUM_MASK                        (0xffffUL<<16)
#define DEV_UDSP_CHNn_CFG1_BANK_NUM_MASK                        (0xffffUL<<0)
/****uDSP_CHNn_CFG1 end****/


/***********************************uDSP_EN***********************************/
#define DEV_UDSP_EN_CHN_EN_WE_MASK                              (0xffUL<<16)
#define DEV_UDSP_EN_CHN_EN_MASK                                 (0xffUL<<0)
/****uDSP_EN end****/


/***********************************uDSP_IE***********************************/
#define DEV_UDSP_IE_FFT_BIT32_OF                                (0x1UL<<17)
#define DEV_UDSP_IE_FFT_BIT31_OF                                (0x1UL<<16)
#define DEV_UDSP_IE_END_MASK                                    (0xffUL<<0)
/****uDSP_IE end****/


/***********************************uDSP_PD***********************************/
#define DEV_UDSP_PD_FFT_BIT32_OF                                (0x1UL<<17)
#define DEV_UDSP_PD_FFT_BIT31_OF                                (0x1UL<<16)
#define DEV_UDSP_PD_END_MASK                                    (0xffUL<<0)
/****uDSP_PD end****/


/***********************************uDSP_BIST_CFG***********************************/
#define DEV_UDSP_BIST_CFG_BUF1_BIST_LS_DISABLE                  (0x0UL<<13)
#define DEV_UDSP_BIST_CFG_BUF1_BIST_LS_ENABLE                   (0x1UL<<13)
#define DEV_UDSP_BIST_CFG_BUF1_BIST_LS_MASK                     (0x1UL<<13)
#define DEV_UDSP_BIST_CFG_BUF1_RME_DISABLE                      (0x0UL<<12)
#define DEV_UDSP_BIST_CFG_BUF1_RME_ENABLE                       (0x1UL<<12)
#define DEV_UDSP_BIST_CFG_BUF1_RME_MASK                         (0x1UL<<12)
#define DEV_UDSP_BIST_CFG_BUF1_RM_MASK                          (0xfUL<<8)
#define DEV_UDSP_BIST_CFG_BUF0_BIST_LS_DISABLE                  (0x0UL<<5)
#define DEV_UDSP_BIST_CFG_BUF0_BIST_LS_ENABLE                   (0x1UL<<5)
#define DEV_UDSP_BIST_CFG_BUF0_BIST_LS_MASK                     (0x1UL<<5)
#define DEV_UDSP_BIST_CFG_BUF0_RME_DISABLE                      (0x0UL<<4)
#define DEV_UDSP_BIST_CFG_BUF0_RME_ENABLE                       (0x1UL<<4)
#define DEV_UDSP_BIST_CFG_BUF0_RME_MASK                         (0x1UL<<4)
#define DEV_UDSP_BIST_CFG_BUF0_RM_MASK                          (0xfUL<<0)
/****uDSP_BIST_CFG end****/


/***********************************uDSP_BIST_EN***********************************/
#define DEV_UDSP_BIST_EN_BUF1_BIST_EN_DISABLE                   (0x0UL<<1)
#define DEV_UDSP_BIST_EN_BUF1_BIST_EN_ENABLE                    (0x1UL<<1)
#define DEV_UDSP_BIST_EN_BUF1_BIST_EN_MASK                      (0x1UL<<1)
#define DEV_UDSP_BIST_EN_BUF0_BIST_EN_DISABLE                   (0x0UL<<0)
#define DEV_UDSP_BIST_EN_BUF0_BIST_EN_ENABLE                    (0x1UL<<0)
#define DEV_UDSP_BIST_EN_BUF0_BIST_EN_MASK                      (0x1UL<<0)
/****uDSP_BIST_EN end****/


/***********************************uDSP_BIST_DONE***********************************/
#define DEV_UDSP_BIST_DONE_BUF1_BIST_DONE_BISTBUSY              (0x0UL<<1)
#define DEV_UDSP_BIST_DONE_BUF1_BIST_DONE_BISTDONE              (0x1UL<<1)
#define DEV_UDSP_BIST_DONE_BUF1_BIST_DONE_MASK                  (0x1UL<<1)
#define DEV_UDSP_BIST_DONE_BUF0_BIST_DONE_BISTBUSY              (0x0UL<<0)
#define DEV_UDSP_BIST_DONE_BUF0_BIST_DONE_BISTDONE              (0x1UL<<0)
#define DEV_UDSP_BIST_DONE_BUF0_BIST_DONE_MASK                  (0x1UL<<0)
/****uDSP_BIST_DONE end****/


/***********************************uDSP_BIST_FAIL***********************************/
#define DEV_UDSP_BIST_FAIL_BUF1_BIST_FAIL_BISTBUSYORBISTOK      (0x0UL<<1)
#define DEV_UDSP_BIST_FAIL_BUF1_BIST_FAIL_BISTFAIL              (0x1UL<<1)
#define DEV_UDSP_BIST_FAIL_BUF1_BIST_FAIL_MASK                  (0x1UL<<1)
#define DEV_UDSP_BIST_FAIL_BUF0_BIST_FAIL_BISTBUSYORBISTOK      (0x0UL<<0)
#define DEV_UDSP_BIST_FAIL_BUF0_BIST_FAIL_BISTFAIL              (0x1UL<<0)
#define DEV_UDSP_BIST_FAIL_BUF0_BIST_FAIL_MASK                  (0x1UL<<0)
/****uDSP_BIST_FAIL end****/


/***********************************uDSP_CHN register***********************************/
typedef struct
{
    __IO    uint32_t    SLA;                                     /* 0x0    uDSP Channel 0 Source Lower ADDR */
    __IO    uint32_t    SUA;                                     /* 0x4    uDSP Channel 0 Source Upper ADDR */
    __IO    uint32_t    SCA;                                     /* 0x8    uDSP Channel 0 Source Current ADDR */
    __IO    uint32_t    SMF;                                     /* 0xc    uDSP Channel 0 Source Memory Format */
    __IO    uint32_t    DLA;                                     /* 0x10    uDSP Channel 0 Destination Lower ADDR */
    __IO    uint32_t    DUA;                                     /* 0x14    uDSP Channel 0 Destination Upper ADDR */
    __IO    uint32_t    DCA;                                     /* 0x18    uDSP Channel 0 Destination Current ADDR */
    __IO    uint32_t    DMF;                                     /* 0x1c    uDSP Channel 0 Destination Memory Format */
    __IO    uint32_t    LMF0;                                    /* 0x20    uDSP Channel 0 Local Memory Format 0 */
    __IO    uint32_t    LMF1;                                    /* 0x24    uDSP Channel 0 Local Memory Format 1 */
    __IO    uint32_t    LMF2;                                    /* 0x28    uDSP Channel 0 Local Memory Format 2 */
    __IO    uint32_t    LMF3;                                    /* 0x2c    uDSP Channel 0 Local Memory Format 3 */
    __IO    uint32_t    LMF4;                                    /* 0x30    uDSP Channel 0 Local Memory Format 4 */
    uint32_t    RESERVED0[19];
    __IO    uint32_t    CFG0;                                    /* 0x80    uDSP Channel 0 Configure 0 */
    __IO    uint32_t    CFG1;                                    /* 0x84    uDSP Channel 0 Configure 1 */
    uint32_t    RESERVED1[30];
} uDSP_CHN_RegDef;
/****uDSP_CHN end****/

/***********************************DEV_UDSP register***********************************/
typedef struct
{
    uDSP_CHN_RegDef    CHN[8];                                  /* 0x0    uDSP Channel 0 Source Lower ADDR */
    uint32_t    RESERVED0[512];
    __IO    uint32_t    EN;                                      /* 0x1000    uDSP Channel 1 Source Upper ADDR */
    __IO    uint32_t    IE;                                      /* 0x1004    uDSP Channel 1 Source Memory Format */
    __IO    uint32_t    PD;                                      /* 0x1008    uDSP Channel 1 Destination Upper ADDR */
    uint32_t    RESERVED1[1021];
    __IO    uint32_t    BIST_CFG;                                /* 0x2000    uDSP Channel 1 Destination Memory Format */
    __IO    uint32_t    BIST_EN;                                 /* 0x2004    uDSP Channel 1 Local Memory Format 1 */
    __I     uint32_t    BIST_DONE;                               /* 0x2008    uDSP Channel 1 Local Memory Format 3 */
    __I     uint32_t    BIST_FAIL;                               /* 0x200c    uDSP Channel 1 Configure 0 */
} DEV_UDSP_RegDef;
/****DEV_UDSP end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
