/*
 * Copyright (c) 2012-2019 Andes Technology Corporation
 * All rights reserved.
 *
 */

#ifndef __PLATFORM_H__
#define __PLATFORM_H__

#ifdef __cplusplus
extern "C" {
#endif
#include <stddef.h>
#include "core_v5.h"
#include "sp2cw3.h"
#include "hal_common.h"
/* ============== Add peripheral header reference here ====================== */

#include "base_space.h"
/* ========================================================================== */
#include "interrupt.h"
/*****************************************************************************
 * Flash Header Definitions
 ****************************************************************************/
#define  NUM_OF_BINS	4

typedef struct {
	__I uint32_t NAME;
	__I uint32_t ADDR;
	__I uint32_t SIZE;
	__I uint32_t CHECKSUM;
} BIN_INFO_Def;

typedef struct {
	__I uint32_t JUMP_CODE; 				/* Jump Code: 	*/
	__I uint32_t TAG_MAGIC; 				/* Tag Magic: 	*/
	__I uint32_t ENCRY_ADDR;					/* Tag Size: 	*/
	__I uint32_t USER_FLAG; 				/* User Flag: 	*/

	__I uint32_t ENCRY_SIZE; 					/* SSP Version: */
	__I uint32_t BUILD_DATE;				/* __DATE__ String Address 	*/
	__I uint32_t BUILD_TIME;				/* __TIME__ String Address 	*/
	__I uint32_t TOTAL_BINS;				/* Total Bins */

	__I BIN_INFO_Def BIN[NUM_OF_BINS];
} HEADER_Def;

#define	  HEADER_BASE			 _IO_(0x4C000000)
#define   FW_HEADER              ((HEADER_Def *) HEADER_BASE)
/*****************************************************************************
 * IRQ Definitions
 *****************************************************************************/

#define  NUM_OF_IRQ	42
typedef struct {
	__IO uint32_t TRAP_ENTRY;
	__IO uint32_t IRQ_ENTRY[NUM_OF_IRQ];
} IRQn_Table_Def;

extern int8_t vector_base;
#define	  VTABLE_BASE	_IO_(&vector_base)
#define   VTABLE    	((IRQn_Table_Def *) VTABLE_BASE)

/*****************************************************************************
 * Peripheral device HAL declaration
 ****************************************************************************/

#define   CSR_MMU                   ((CSR_MMU_RegDef *) CSR_MMU_BASE)
#define   DEV_UDSP                ((DEV_UDSP_RegDef_f *) DEV_UDSP_BASE)
#define   DEV_DMAC                ((DEV_DMAC_RegDef_f *) DEV_DMAC_BASE)
#define   DEV_NPU                   ((DEV_NPU_RegDef_f *) DEV_NPU_BASE)
#define   DEV_MEMC                ((DEV_MEMC_RegDef_f *) DEV_MEMC_BASE)
#define   DEV_CACHE             ((DEV_CACHE_RegDef_f *) DEV_CACHE_BASE)
#define   DEV_NORC                ((DEV_NORC_RegDef_f *) DEV_NORC_BASE)
#define   DEV_MPU                   ((DEV_MPU_RegDef_f *) DEV_MPU_BASE)
#define   PSRAM_RWC             ((PSRAM_RWC_RegDef_f *) PSRAM_RWC_BASE)
#define   DEV_CHIP                ((DEV_CHIP_RegDef_f *) DEV_CHIP_BASE)
#define   DEV_CMU                   ((DEV_CMU_RegDef_f *) DEV_CMU_BASE)
#define   DEV_RMU                   ((DEV_RMU_RegDef_f *) DEV_RMU_BASE)
#define   DEV_WFI                   ((DEV_WFI_RegDef_f *) DEV_WFI_BASE)
#define   DEV_UREG                ((DEV_UREG_RegDef_f *) DEV_UREG_BASE)
#define   DEV_GLOBAL          ((DEV_GLOBAL_RegDef_f *) DEV_GLOBAL_BASE)
#define   DEV_TIMER             ((DEV_TIMER_RegDef_f *) DEV_TIMER_BASE)
#define   DEV_EFUSE             ((DEV_EFUSE_RegDef_f *) DEV_EFUSE_BASE)
#define   AON_OSC                   ((AON_OSC_RegDef_f *) AON_OSC_BASE)
#define   AON_PLL                   ((AON_PLL_RegDef_f *) AON_PLL_BASE)
#define   AON_CMU                   ((AON_CMU_RegDef_f *) AON_CMU_BASE)
#define   AON_PMU                   ((AON_PMU_RegDef_f *) AON_PMU_BASE)
#define   AON_RMU                   ((AON_RMU_RegDef_f *) AON_RMU_BASE)
#define   AON_GPIO                ((AON_GPIO_RegDef_f *) AON_GPIO_BASE)
#define   AON_MEM                   ((AON_MEM_RegDef_f *) AON_MEM_BASE)
#define   AON_GLOBAL          ((AON_GLOBAL_RegDef_f *) AON_GLOBAL_BASE)
#define   AON_LRADC             ((AON_LRADC_RegDef_f *) AON_LRADC_BASE)
#define   AON_AUDI                ((AON_AUDI_RegDef_f *) AON_AUDI_BASE)
#define   DEV_SPI0                   ((DEV_SPIn_RegDef_f *) DEV_SPI0_BASE)
#define   DEV_SPI1                   ((DEV_SPIn_RegDef_f *) DEV_SPI1_BASE)
#define   DEV_PWM                   ((DEV_PWM_RegDef_f *) DEV_PWM_BASE)
#define   DEV_CAMERA          ((DEV_CAMERA_RegDef_f *) DEV_CAMERA_BASE)
#define   DEV_UART0             ((DEV_UARTn_RegDef_f *) DEV_UART0_BASE)
#define   DEV_UART1             ((DEV_UARTn_RegDef_f *) DEV_UART1_BASE)
#define   DEV_UART2             ((DEV_UARTn_RegDef_f *) DEV_UART2_BASE)
#define   DEV_UART3             ((DEV_UARTn_RegDef_f *) DEV_UART3_BASE)
#define   DEV_IIC0                ((DEV_IICn_RegDef_f *) DEV_IIC0_BASE)
#define   DEV_IIC1                ((DEV_IICn_RegDef_f *) DEV_IIC1_BASE)
#define   DEV_ASI0                ((DEV_ASIn_RegDef_f *) DEV_ASI0_BASE)
#define   DEV_ASI1                ((DEV_ASIn_RegDef_f *) DEV_ASI1_BASE)
#define   IR_RX                         ((IR_RX_RegDef_f *) IR_RX_BASE)
#define   DEV_ADC                   ((DEV_ADC_RegDef_f *) DEV_ADC_BASE)
#define   DEV_DAC                   ((DEV_DAC_RegDef_f *) DEV_DAC_BASE)
#define   DEV_SRC                   ((DEV_SRC_RegDef_f *) DEV_SRC_BASE)
#define   DEV_GPIO                ((DEV_GPIO_RegDef_f *) DEV_GPIO_BASE)

/*****************************************************************************
 * Board specified
 ****************************************************************************/

extern __GLOBAL SOC_RUNTIME RUNTIME_SPV40;

void MTIME_DelayTicks(uint32_t ticks);
void mtime_config(uint32_t period_in_us);
uint32_t mtime_get_clock(void);


#define	cpu_mstatus_alloc()		int32_t mstatus = 0
#define cpu_enter_critical()	do{mstatus = __nds__read_csr(NDS_MSTATUS);	GIE_DISABLE();}while(0)
#define cpu_exit_critical()		do{__nds__write_csr(mstatus,NDS_MSTATUS);}while(0)

#ifdef __cplusplus
}
#endif

#endif	/* __PLATFORM_H__ */
