#ifndef __DEV_SRC_H__
#define __DEV_SRC_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************SRC_CHNn_LSR***********************************/
#define DEV_SRC_CHNn_LSR_MASK                                   (0xffffffffUL<<0)
/****SRC_CHNn_LSR end****/


/***********************************SRC_CHNn_USR***********************************/
#define DEV_SRC_CHNn_USR_MASK                                   (0xffffffffUL<<0)
/****SRC_CHNn_USR end****/


/***********************************SRC_CHNn_LTH***********************************/
#define DEV_SRC_CHNn_LTH_MASK                                   (0xfffUL<<0)
/****SRC_CHNn_LTH end****/


/***********************************SRC_CHNn_UTH***********************************/
#define DEV_SRC_CHNn_UTH_MASK                                   (0xfffUL<<0)
/****SRC_CHNn_UTH end****/


/***********************************SRC_CHNn_CFG***********************************/
#define DEV_SRC_CHNn_CFG_OUTPUT_FMT_HIGH16BIT                   (0x0UL<<26)
#define DEV_SRC_CHNn_CFG_OUTPUT_FMT_LOW_16BIT                   (0x1UL<<26)
#define DEV_SRC_CHNn_CFG_OUTPUT_FMT_HIGH24BIT                   (0x2UL<<26)
#define DEV_SRC_CHNn_CFG_OUTPUT_FMT_LOW_24BIT                   (0x3UL<<26)
#define DEV_SRC_CHNn_CFG_OUTPUT_FMT_MASK                        (0x3UL<<26)
#define DEV_SRC_CHNn_CFG_INPUT_FMT_HIGH16BIT                    (0x0UL<<24)
#define DEV_SRC_CHNn_CFG_INPUT_FMT_LOW_16BIT                    (0x1UL<<24)
#define DEV_SRC_CHNn_CFG_INPUT_FMT_HIGH24BIT                    (0x2UL<<24)
#define DEV_SRC_CHNn_CFG_INPUT_FMT_LOW_24BIT                    (0x3UL<<24)
#define DEV_SRC_CHNn_CFG_INPUT_FMT_MASK                         (0x3UL<<24)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL3_23                          (0x0UL<<22)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL3_24                          (0x1UL<<22)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL3_25                          (0x2UL<<22)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL3_MASK                        (0x3UL<<22)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL2_19                          (0x0UL<<20)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL2_20                          (0x1UL<<20)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL2_21                          (0x2UL<<20)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL2_22                          (0x3UL<<20)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL2_MASK                        (0x3UL<<20)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL1_18                          (0x0UL<<18)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL1_19                          (0x1UL<<18)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL1_20                          (0x2UL<<18)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL1_21                          (0x3UL<<18)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL1_MASK                        (0x3UL<<18)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL0_19                          (0x0UL<<16)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL0_20                          (0x1UL<<16)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL0_21                          (0x2UL<<16)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL0_22                          (0x3UL<<16)
#define DEV_SRC_CHNn_CFG_SHIFT_SEL0_MASK                        (0x3UL<<16)
#define DEV_SRC_CHNn_CFG_WBUF_HALF_LVL_256                      (0x0UL<<12)
#define DEV_SRC_CHNn_CFG_WBUF_HALF_LVL_512                      (0x1UL<<12)
#define DEV_SRC_CHNn_CFG_WBUF_HALF_LVL_768                      (0x2UL<<12)
#define DEV_SRC_CHNn_CFG_WBUF_HALF_LVL_1024                     (0x3UL<<12)
#define DEV_SRC_CHNn_CFG_WBUF_HALF_LVL_MASK                     (0x3UL<<12)
#define DEV_SRC_CHNn_CFG_RX_DEV_SEL_DEV0RXFIFO                  (0x0UL<<8)
#define DEV_SRC_CHNn_CFG_RX_DEV_SEL_DEV1RXFIFO                  (0x1UL<<8)
#define DEV_SRC_CHNn_CFG_RX_DEV_SEL_DEV2RXFIFO                  (0x2UL<<8)
#define DEV_SRC_CHNn_CFG_RX_DEV_SEL_DEV3RXFIFO                  (0x3UL<<8)
#define DEV_SRC_CHNn_CFG_RX_DEV_SEL_DEV4RXFIFO                  (0x4UL<<8)
#define DEV_SRC_CHNn_CFG_RX_DEV_SEL_DEV5RXFIFO                  (0x5UL<<8)
#define DEV_SRC_CHNn_CFG_RX_DEV_SEL_DEV6RXFIFO                  (0x6UL<<8)
#define DEV_SRC_CHNn_CFG_RX_DEV_SEL_DEV7RXFIFO                  (0x7UL<<8)
#define DEV_SRC_CHNn_CFG_RX_DEV_SEL_MASK                        (0x7UL<<8)
#define DEV_SRC_CHNn_CFG_TX_DEV_SEL_DEV0TXFIFO                  (0x0UL<<4)
#define DEV_SRC_CHNn_CFG_TX_DEV_SEL_DEV1TXFIFO                  (0x1UL<<4)
#define DEV_SRC_CHNn_CFG_TX_DEV_SEL_DEV2TXFIFO                  (0x2UL<<4)
#define DEV_SRC_CHNn_CFG_TX_DEV_SEL_DEV3TXFIFO                  (0x3UL<<4)
#define DEV_SRC_CHNn_CFG_TX_DEV_SEL_DEV4TXFIFO                  (0x4UL<<4)
#define DEV_SRC_CHNn_CFG_TX_DEV_SEL_DEV5TXFIFO                  (0x5UL<<4)
#define DEV_SRC_CHNn_CFG_TX_DEV_SEL_DEV6TXFIFO                  (0x6UL<<4)
#define DEV_SRC_CHNn_CFG_TX_DEV_SEL_DEV7TXFIFO                  (0x7UL<<4)
#define DEV_SRC_CHNn_CFG_TX_DEV_SEL_MASK                        (0x7UL<<4)
#define DEV_SRC_CHNn_CFG_MONO_STEREO                            (0x0UL<<3)
#define DEV_SRC_CHNn_CFG_MONO_MONO                              (0x1UL<<3)
#define DEV_SRC_CHNn_CFG_MONO_MASK                              (0x1UL<<3)
#define DEV_SRC_CHNn_CFG_CBUF_EN_DISABLE                        (0x0UL<<2)
#define DEV_SRC_CHNn_CFG_CBUF_EN_ENABLE                         (0x1UL<<2)
#define DEV_SRC_CHNn_CFG_CBUF_EN_MASK                           (0x1UL<<2)
#define DEV_SRC_CHNn_CFG_MODE_SEL_SOFTSRC                       (0x0UL<<1)
#define DEV_SRC_CHNn_CFG_MODE_SEL_HARDSRC                       (0x1UL<<1)
#define DEV_SRC_CHNn_CFG_MODE_SEL_MASK                          (0x1UL<<1)
#define DEV_SRC_CHNn_CFG_Enable_DISABLE                         (0x0UL<<0)
#define DEV_SRC_CHNn_CFG_Enable_ENABLE                          (0x1UL<<0)
#define DEV_SRC_CHNn_CFG_Enable_MASK                            (0x1UL<<0)
/****SRC_CHNn_CFG end****/


/***********************************SRC_CHNn_IE***********************************/
#define DEV_SRC_CHNn_IE_WBUF_AE                                 (0x1UL<<5)
#define DEV_SRC_CHNn_IE_WBUF_AF                                 (0x1UL<<4)
#define DEV_SRC_CHNn_IE_RX_FIFO_UF                              (0x1UL<<3)
#define DEV_SRC_CHNn_IE_TX_FIFO_OF                              (0x1UL<<2)
#define DEV_SRC_CHNn_IE_RX_FIFO_HFUL                            (0x1UL<<1)
#define DEV_SRC_CHNn_IE_TX_FIFO_HEMP                            (0x1UL<<0)
/****SRC_CHNn_IE end****/


/***********************************SRC_CHNn_PD***********************************/
#define DEV_SRC_CHNn_PD_WBUF_AE                                 (0x1UL<<5)
#define DEV_SRC_CHNn_PD_WBUF_AF                                 (0x1UL<<4)
#define DEV_SRC_CHNn_PD_RX_FIFO_UF                              (0x1UL<<3)
#define DEV_SRC_CHNn_PD_TX_FIFO_OF                              (0x1UL<<2)
#define DEV_SRC_CHNn_PD_RX_FIFO_HFUL                            (0x1UL<<1)
#define DEV_SRC_CHNn_PD_TX_FIFO_HEMP                            (0x1UL<<0)
/****SRC_CHNn_PD end****/


/***********************************SRC_CHNn_STA***********************************/
#define DEV_SRC_CHNn_STA_RX_FIFO_RLVL_MASK                      (0x7UL<<20)
#define DEV_SRC_CHNn_STA_TX_FIFO_WLVL_MASK                      (0x7UL<<16)
#define DEV_SRC_CHNn_STA_WBUF_AE                                (0x1UL<<13)
#define DEV_SRC_CHNn_STA_WBUF_AF                                (0x1UL<<12)
#define DEV_SRC_CHNn_STA_WBUF_WLVL_MASK                         (0xfffUL<<0)
/****SRC_CHNn_STA end****/


/***********************************SRC_CHNn_CBUF***********************************/
#define DEV_SRC_CHNn_CBUF_MASK                                  (0xffffffUL<<8)
/****SRC_CHNn_CBUF end****/


/***********************************SRC_CHNn_WBUF***********************************/
#define DEV_SRC_CHNn_WBUF_MASK                                  (0xffffffffUL<<0)
/****SRC_CHNn_WBUF end****/


/***********************************SRC_CHNn_RBUF***********************************/
#define DEV_SRC_CHNn_RBUF_MASK                                  (0xffffffffUL<<0)
/****SRC_CHNn_RBUF end****/


/***********************************SRC_BIST_RM***********************************/
#define DEV_SRC_BIST_RM_CHN1_FBUF_RM_MASK                       (0xfUL<<24)
#define DEV_SRC_BIST_RM_CHN1_RBUF_RM_MASK                       (0xfUL<<20)
#define DEV_SRC_BIST_RM_CHN1_CBUF_RM_MASK                       (0xfUL<<16)
#define DEV_SRC_BIST_RM_CHN0_FBUF_RM_MASK                       (0xfUL<<8)
#define DEV_SRC_BIST_RM_CHN0_RBUF_RM_MASK                       (0xfUL<<4)
#define DEV_SRC_BIST_RM_CHN0_CBUF_RM_MASK                       (0xfUL<<0)
/****SRC_BIST_RM end****/


/***********************************SRC_BIST_EN***********************************/
#define DEV_SRC_BIST_EN_CHN1_FBUF_LS_DISABLE                    (0x0UL<<26)
#define DEV_SRC_BIST_EN_CHN1_FBUF_LS_ENABLE                     (0x1UL<<26)
#define DEV_SRC_BIST_EN_CHN1_FBUF_LS_MASK                       (0x1UL<<26)
#define DEV_SRC_BIST_EN_CHN1_RBUF_LS_DISABLE                    (0x0UL<<25)
#define DEV_SRC_BIST_EN_CHN1_RBUF_LS_ENABLE                     (0x1UL<<25)
#define DEV_SRC_BIST_EN_CHN1_RBUF_LS_MASK                       (0x1UL<<25)
#define DEV_SRC_BIST_EN_CHN1_CBUF_LS_DISABLE                    (0x0UL<<24)
#define DEV_SRC_BIST_EN_CHN1_CBUF_LS_ENABLE                     (0x1UL<<24)
#define DEV_SRC_BIST_EN_CHN1_CBUF_LS_MASK                       (0x1UL<<24)
#define DEV_SRC_BIST_EN_CHN1_FBUF_RME_DISABLE                   (0x0UL<<21)
#define DEV_SRC_BIST_EN_CHN1_FBUF_RME_ENABLE                    (0x1UL<<21)
#define DEV_SRC_BIST_EN_CHN1_FBUF_RME_MASK                      (0x1UL<<21)
#define DEV_SRC_BIST_EN_CHN1_FBUF_EN_DISABLE                    (0x0UL<<20)
#define DEV_SRC_BIST_EN_CHN1_FBUF_EN_ENABLE                     (0x1UL<<20)
#define DEV_SRC_BIST_EN_CHN1_FBUF_EN_MASK                       (0x1UL<<20)
#define DEV_SRC_BIST_EN_CHN1_RBUF_RME_DISABLE                   (0x0UL<<19)
#define DEV_SRC_BIST_EN_CHN1_RBUF_RME_ENABLE                    (0x1UL<<19)
#define DEV_SRC_BIST_EN_CHN1_RBUF_RME_MASK                      (0x1UL<<19)
#define DEV_SRC_BIST_EN_CHN1_RBUF_EN_DISABLE                    (0x0UL<<18)
#define DEV_SRC_BIST_EN_CHN1_RBUF_EN_ENABLE                     (0x1UL<<18)
#define DEV_SRC_BIST_EN_CHN1_RBUF_EN_MASK                       (0x1UL<<18)
#define DEV_SRC_BIST_EN_CHN1_CBUF_RME_DISABLE                   (0x0UL<<17)
#define DEV_SRC_BIST_EN_CHN1_CBUF_RME_ENABLE                    (0x1UL<<17)
#define DEV_SRC_BIST_EN_CHN1_CBUF_RME_MASK                      (0x1UL<<17)
#define DEV_SRC_BIST_EN_CHN1_CBUF_EN_DISABLE                    (0x0UL<<16)
#define DEV_SRC_BIST_EN_CHN1_CBUF_EN_ENABLE                     (0x1UL<<16)
#define DEV_SRC_BIST_EN_CHN1_CBUF_EN_MASK                       (0x1UL<<16)
#define DEV_SRC_BIST_EN_CHN0_FBUF_LS_DISABLE                    (0x0UL<<10)
#define DEV_SRC_BIST_EN_CHN0_FBUF_LS_ENABLE                     (0x1UL<<10)
#define DEV_SRC_BIST_EN_CHN0_FBUF_LS_MASK                       (0x1UL<<10)
#define DEV_SRC_BIST_EN_CHN0_WBUF_LS_DISABLE                    (0x0UL<<9)
#define DEV_SRC_BIST_EN_CHN0_WBUF_LS_ENABLE                     (0x1UL<<9)
#define DEV_SRC_BIST_EN_CHN0_WBUF_LS_MASK                       (0x1UL<<9)
#define DEV_SRC_BIST_EN_CHN0_CBUF_LS_DISABLE                    (0x0UL<<8)
#define DEV_SRC_BIST_EN_CHN0_CBUF_LS_ENABLE                     (0x1UL<<8)
#define DEV_SRC_BIST_EN_CHN0_CBUF_LS_MASK                       (0x1UL<<8)
#define DEV_SRC_BIST_EN_CHN0_FBUF_RME_DISABLE                   (0x0UL<<5)
#define DEV_SRC_BIST_EN_CHN0_FBUF_RME_ENABLE                    (0x1UL<<5)
#define DEV_SRC_BIST_EN_CHN0_FBUF_RME_MASK                      (0x1UL<<5)
#define DEV_SRC_BIST_EN_CHN0_FBUF_EN_DISABLE                    (0x0UL<<4)
#define DEV_SRC_BIST_EN_CHN0_FBUF_EN_ENABLE                     (0x1UL<<4)
#define DEV_SRC_BIST_EN_CHN0_FBUF_EN_MASK                       (0x1UL<<4)
#define DEV_SRC_BIST_EN_CHN0_WBUF_RME_DISABLE                   (0x0UL<<3)
#define DEV_SRC_BIST_EN_CHN0_WBUF_RME_ENABLE                    (0x1UL<<3)
#define DEV_SRC_BIST_EN_CHN0_WBUF_RME_MASK                      (0x1UL<<3)
#define DEV_SRC_BIST_EN_CHN0_WBUF_EN_DISABLE                    (0x0UL<<2)
#define DEV_SRC_BIST_EN_CHN0_WBUF_EN_ENABLE                     (0x1UL<<2)
#define DEV_SRC_BIST_EN_CHN0_WBUF_EN_MASK                       (0x1UL<<2)
#define DEV_SRC_BIST_EN_CHN0_CBUF_RME_DISABLE                   (0x0UL<<1)
#define DEV_SRC_BIST_EN_CHN0_CBUF_RME_ENABLE                    (0x1UL<<1)
#define DEV_SRC_BIST_EN_CHN0_CBUF_RME_MASK                      (0x1UL<<1)
#define DEV_SRC_BIST_EN_CHN0_CBUF_EN_DISABLE                    (0x0UL<<0)
#define DEV_SRC_BIST_EN_CHN0_CBUF_EN_ENABLE                     (0x1UL<<0)
#define DEV_SRC_BIST_EN_CHN0_CBUF_EN_MASK                       (0x1UL<<0)
/****SRC_BIST_EN end****/


/***********************************SRC_BIST_DONE***********************************/
#define DEV_SRC_BIST_DONE_CHN1_FBUF_DONE                        (0x1UL<<18)
#define DEV_SRC_BIST_DONE_CHN1_DBUF_DONE                        (0x1UL<<17)
#define DEV_SRC_BIST_DONE_CHN1_CBUF_DONE                        (0x1UL<<16)
#define DEV_SRC_BIST_DONE_CHN0_FBUF_DONE                        (0x1UL<<2)
#define DEV_SRC_BIST_DONE_CHN0_DBUF_DONE                        (0x1UL<<1)
#define DEV_SRC_BIST_DONE_CHN0_CBUF_DONE                        (0x1UL<<0)
/****SRC_BIST_DONE end****/


/***********************************SRC_BIST_FAIL***********************************/
#define DEV_SRC_BIST_FAIL_CHN1_FBUF_FAIL                        (0x1UL<<18)
#define DEV_SRC_BIST_FAIL_CHN1_DBUF_FAIL                        (0x1UL<<17)
#define DEV_SRC_BIST_FAIL_CHN1_CBUF_FAIL                        (0x1UL<<16)
#define DEV_SRC_BIST_FAIL_CHN0_FBUF_FAIL                        (0x1UL<<2)
#define DEV_SRC_BIST_FAIL_CHN0_DBUF_FAIL                        (0x1UL<<1)
#define DEV_SRC_BIST_FAIL_CHN0_CBUF_FAIL                        (0x1UL<<0)
/****SRC_BIST_FAIL end****/


/***********************************SRC_CHN register***********************************/
typedef struct
{

    __IO    uint32_t    LSR;                                     /* 0x0    SRC CHNn Lower Sample-Rate Ratio */
    __IO    uint32_t    USR;                                     /* 0x4    SRC CHNn Upper Sample-Rate Ratio */
    __IO    uint32_t    LTH;                                     /* 0x8    SRC CHNn Lower Threshold */
    __IO    uint32_t    UTH;                                     /* 0xc    SRC CHNn Upper Threshold */
    __IO    uint32_t    CFG;                                     /* 0x10    SRC CHNn Configure */
    __IO    uint32_t    IE;                                      /* 0x14    SRC CHNn Interrupt Enable */
    __IO    uint32_t    PD;                                      /* 0x18    SRC CHNn Interrupt Pending */
    __I     uint32_t    STA;                                     /* 0x1c    SRC CHNn Status */
    __IO    uint32_t    CBUF;                                    /* 0x20    SRC CHNn COE buffer */
    __O     uint32_t    WBUF;                                    /* 0x24    SRC CHNn Data Input buffer */
    __I     uint32_t    RBUF;                                    /* 0x28    SRC CHNn Data Output buffer */
    uint32_t    RESERVED0[53];
} SRC_CHN_RegDef;
/****SRC_CHN end****/

/***********************************DEV_SRC register***********************************/
typedef struct
{

    SRC_CHN_RegDef    CHN[2];                                  /* 0x0    SRC CHNn Lower Sample-Rate Ratio */
    uint32_t    RESERVED0[896];
    __IO    uint32_t    BIST_RM;                                 /* 0x1000    SRC CHNn Configure */
    __IO    uint32_t    BIST_EN;                                 /* 0x1004    SRC CHNn Interrupt Pending */
    __I     uint32_t    BIST_DONE;                               /* 0x1008    SRC CHNn COE buffer */
    __I     uint32_t    BIST_FAIL;                               /* 0x100c    SRC CHNn Data Output buffer */
} DEV_SRC_RegDef;
/****DEV_SRC end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
