#ifndef __DEV_ADC_FIELD_H__
#define __DEV_ADC_FIELD_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************CHNn_CFG***********************************/
typedef struct
{

    __IO uint32_t CHN_EN              : 1;
    __IO uint32_t MODE_SEL            : 1;
    __IO uint32_t CIC_SEL             : 2;
    __IO uint32_t CIC_CLK_SEL         : 1;
    __IO uint32_t CIC_DAT_SEL         : 1;
    __IO uint32_t CIC_CLK_DIV         : 2;
    __IO uint32_t FIR_CLK_SEL         : 1;
    __IO uint32_t FIR_CLK_DIV         : 3;
    __IO uint32_t VOL                 : 4;
    __IO uint32_t HPF_EN              : 1;
    __IO uint32_t HPF_COEF            : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t CIC_CLK_PHASE       : 1;
    __IO uint32_t DMIC_DLY_SEL        : 2;
    __IO uint32_t DMIC_CLK_DIV        : 3;
    __IO uint32_t DMIC_PIN_SEL        : 1;
    __IO uint32_t MIX_SRC_SEL         : 2;
    __IO uint32_t MIX_GAIN            : 1;
    uint32_t RESERVED1           : 1;
} DEV_ADC_CHNn_CFG_Field;
/****DEV_ADCCHNn_CFG end****/

/***********************************CFG***********************************/
typedef struct
{

    uint32_t RESERVED0           : 6;
    __IO uint32_t ADC_WIDTH           : 1;
    uint32_t RESERVED1           : 1;
    __IO uint32_t HFUL_TH             : 6;
    uint32_t RESERVED2           : 2;
    __IO uint32_t DBG_IN_EN           : 1;
    __IO uint32_t DBG_OUT_EN          : 1;
    __IO uint32_t DBG_CHN_SEL         : 2;
    __IO uint32_t FIFO_CLK_SEL        : 2;
    uint32_t RESERVED3           : 2;
    __IO uint32_t FIFO_DAT_SEL        : 4;
    uint32_t RESERVED4           : 4;
} DEV_ADC_CFG_Field;
/****DEV_ADCCFG end****/

/***********************************CTL***********************************/
typedef struct
{

    __IO uint32_t ADC_EN              : 1;
    __IO uint32_t DMA_EN              : 1;
    __IO uint32_t SRC_SEL             : 1;
    __IO uint32_t RX_FIFO_RST         : 1;
    uint32_t RESERVED0           : 28;
} DEV_ADC_CTL_Field;
/****DEV_ADCCTL end****/

/***********************************IE***********************************/
typedef struct
{

    __IO uint32_t RX_IRQ              : 1;
    __IO uint32_t RX_FIFO_OF          : 1;
    __IO uint32_t RX_FIFO_UF          : 1;
    uint32_t RESERVED0           : 29;
} DEV_ADC_IE_Field;
/****DEV_ADCIE end****/

/***********************************PD***********************************/
typedef struct
{

    __IO uint32_t RX_IRQ              : 1;
    __IO uint32_t RX_FIFO_OF          : 1;
    __IO uint32_t RX_FIFO_UF          : 1;
    uint32_t RESERVED0           : 29;
} DEV_ADC_PD_Field;
/****DEV_ADCPD end****/

/***********************************STA***********************************/
typedef struct
{

    __I  uint32_t RX_FIFO_RLVL        : 6;
    uint32_t RESERVED0           : 2;
    __I  uint32_t RX_FIFO_HEMP        : 1;
    __I  uint32_t RX_FIFO_EMPT        : 1;
    __I  uint32_t RX_FIFO_HFUL        : 1;
    __I  uint32_t RX_FIFO_FULL        : 1;
    uint32_t RESERVED1           : 20;
} DEV_ADC_STA_Field;
/****DEV_ADCSTA end****/

/***********************************RBUF***********************************/
typedef struct
{

    uint32_t RESERVED0           : 8;
    __I  uint32_t RBUF                : 24;
} DEV_ADC_RBUF_Field;
/****DEV_ADCRBUF end****/

/***********************************GAIN_CFG***********************************/
typedef struct
{

    __IO uint32_t AGC_EN              : 1;
    __IO uint32_t NOISE_GATE_EN       : 1;
    __IO uint32_t Hysteresis          : 2;
    __IO uint32_t Min_gain            : 4;
    __IO uint32_t Max_gain            : 4;
    uint32_t RESERVED0           : 4;
    __IO uint32_t Noise_level         : 8;
    __IO uint32_t Target_level        : 8;
} DEV_ADC_GAIN_CFG_Field;
/****DEV_ADCGAIN_CFG end****/

/***********************************PEAK_AT***********************************/
typedef struct
{

    __IO uint32_t ATTACK_TIME         : 32;
} DEV_ADC_PEAK_AT_Field;
/****DEV_ADCPEAK_AT end****/

/***********************************PEAK_RT***********************************/
typedef struct
{

    __IO uint32_t RELEASE_TIME        : 32;
} DEV_ADC_PEAK_RT_Field;
/****DEV_ADCPEAK_RT end****/

/***********************************GAIN_AT***********************************/
typedef struct
{

    __IO uint32_t ATTACK_TIME         : 32;
} DEV_ADC_GAIN_AT_Field;
/****DEV_ADCGAIN_AT end****/

/***********************************GAIN_RT***********************************/
typedef struct
{

    __IO uint32_t RELEASE_TIME        : 32;
} DEV_ADC_GAIN_RT_Field;
/****DEV_ADCGAIN_RT end****/

/***********************************BIST_EN***********************************/
typedef struct
{

    __IO uint32_t CHN0_BIST_EN        : 1;
    __IO uint32_t CHN1_BIST_EN        : 1;
    __IO uint32_t CHN2_BIST_EN        : 1;
    __IO uint32_t CHN3_BIST_EN        : 1;
    __IO uint32_t CHN0_BIST_RME       : 1;
    __IO uint32_t CHN1_BIST_RME       : 1;
    __IO uint32_t CHN2_BIST_RME       : 1;
    __IO uint32_t CHN3_BIST_RME       : 1;
    __IO uint32_t CHN0_BIST_LS        : 1;
    __IO uint32_t CHN1_BIST_LS        : 1;
    __IO uint32_t CHN2_BIST_LS        : 1;
    __IO uint32_t CHN3_BIST_LS        : 1;
    uint32_t RESERVED0           : 20;
} DEV_ADC_BIST_EN_Field;
/****DEV_ADCBIST_EN end****/

/***********************************BIST_RM***********************************/
typedef struct
{

    __IO uint32_t CHN0_RAM_RM         : 4;
    __IO uint32_t CHN1_RAM_RM         : 4;
    __IO uint32_t CHN2_RAM_RM         : 4;
    __IO uint32_t CHN3_RAM_RM         : 4;
    uint32_t RESERVED0           : 16;
} DEV_ADC_BIST_RM_Field;
/****DEV_ADCBIST_RM end****/

/***********************************BIST_DONE***********************************/
typedef struct
{

    __I  uint32_t CHN0_RAM_DONE       : 1;
    __I  uint32_t CHN1_RAM_DONE       : 1;
    __I  uint32_t CHN2_RAM_DONE       : 1;
    __I  uint32_t CHN3_RAM_DONE       : 1;
    uint32_t RESERVED0           : 28;
} DEV_ADC_BIST_DONE_Field;
/****DEV_ADCBIST_DONE end****/

/***********************************BIST_FAIL***********************************/
typedef struct
{

    __I  uint32_t CHN0_RAM_FAIL       : 1;
    __I  uint32_t CHN1_RAM_FAIL       : 1;
    __I  uint32_t CHN2_RAM_FAIL       : 1;
    __I  uint32_t CHN3_RAM_FAIL       : 1;
    uint32_t RESERVED0           : 28;
} DEV_ADC_BIST_FAIL_Field;
/****DEV_ADCBIST_FAIL end****/

/***********************************MIC_CTRL0***********************************/
typedef struct
{

    __IO uint32_t MIC0_EN             : 1;
    uint32_t RESERVED0           : 1;
    __IO uint32_t MIC0_MODE           : 2;
    __IO uint32_t MIC0_GAIN           : 3;
    uint32_t RESERVED1           : 1;
    __IO uint32_t MIC1_EN             : 1;
    uint32_t RESERVED2           : 1;
    __IO uint32_t MIC1_MODE           : 2;
    __IO uint32_t MIC1_GAIN           : 3;
    uint32_t RESERVED3           : 1;
    __IO uint32_t MIC2_EN             : 1;
    uint32_t RESERVED4           : 1;
    __IO uint32_t MIC2_MODE           : 2;
    __IO uint32_t MIC2_GAIN           : 3;
    uint32_t RESERVED5           : 1;
    __IO uint32_t MIC3_EN             : 1;
    uint32_t RESERVED6           : 1;
    __IO uint32_t MIC3_MODE           : 2;
    __IO uint32_t MIC3_GAIN           : 3;
    uint32_t RESERVED7           : 1;
} DEV_ADC_MIC_CTRL0_Field;
/****DEV_ADCMIC_CTRL0 end****/

/***********************************MIC_CTRL1***********************************/
typedef struct
{

    __IO uint32_t MIC_CHOP_EN         : 1;
    __IO uint32_t MIC_VCMI_CHOP_EN    : 1;
    __IO uint32_t MIC_VCMI_SEL        : 1;
    __IO uint32_t MIC_PD_STUP         : 1;
    __IO uint32_t MIC_IBIAS_CTRL      : 2;
    __IO uint32_t MIC_BYP_EN          : 1;
    __IO uint32_t MIC_MIX_BYP_EN      : 1;
    __IO uint32_t MIC_CAP_CHG         : 1;
    uint32_t RESERVED0           : 23;
} DEV_ADC_MIC_CTRL1_Field;
/****DEV_ADCMIC_CTRL1 end****/

/***********************************MIX_CTRL0***********************************/
typedef struct
{

    __IO uint32_t MIX0_EN             : 1;
    __IO uint32_t MIX0_MIC0_EN        : 1;
    __IO uint32_t MIX0_MIC1_EN        : 1;
    __IO uint32_t MIX0_MIC2_EN        : 1;
    __IO uint32_t MIX0_GAIN           : 4;
    __IO uint32_t MIX1_EN             : 1;
    __IO uint32_t MIX1_MIC0_EN        : 1;
    __IO uint32_t MIX1_MIC1_EN        : 1;
    __IO uint32_t MIX1_MIC2_EN        : 1;
    __IO uint32_t MIX1_GAIN           : 4;
    uint32_t RESERVED0           : 16;
} DEV_ADC_MIX_CTRL0_Field;
/****DEV_ADCMIX_CTRL0 end****/

/***********************************MIX_CTRL1***********************************/
typedef struct
{

    __IO uint32_t MIX_CHOP_EN         : 1;
    __IO uint32_t MIX_PD_STUP         : 1;
    __IO uint32_t ZC_COMP_EN          : 1;
    uint32_t RESERVED0           : 1;
    __IO uint32_t MIX_IBIAS_CTRL      : 2;
    uint32_t RESERVED1           : 26;
} DEV_ADC_MIX_CTRL1_Field;
/****DEV_ADCMIX_CTRL1 end****/

/***********************************SDM_CTRL0***********************************/
typedef struct
{

    __IO uint32_t ADC_START           : 1;
    uint32_t RESERVED0           : 31;
} DEV_ADC_SDM_CTRL0_Field;
/****DEV_ADCSDM_CTRL0 end****/

/***********************************SDM_CTRL1***********************************/
typedef struct
{

    __IO uint32_t ADC0_EN             : 1;
    __IO uint32_t ADC1_EN             : 1;
    uint32_t RESERVED0           : 2;
    __IO uint32_t ADC_IBOTA1_CTRL     : 2;
    __IO uint32_t ADC_IBOTA2_CTRL     : 2;
    __IO uint32_t ADC_CHOP_EN         : 1;
    uint32_t RESERVED1           : 1;
    __IO uint32_t ADC_CHOP_DIV        : 2;
    __IO uint32_t ADC_NONOV           : 2;
    __IO uint32_t ADC_DEM_PD          : 1;
    __IO uint32_t ADC_BKDEM_EN        : 1;
    __IO uint32_t ADC_DITHER_EN       : 1;
    uint32_t RESERVED2           : 1;
    __IO uint32_t ADC_DITHER_SEL      : 2;
    __IO uint32_t ADC_AMPDET_DEM      : 1;
    __IO uint32_t ADC_AMPDET_DITHER   : 1;
    __IO uint32_t ADC_VREF_CHG        : 1;
    uint32_t RESERVED3           : 1;
    __IO uint32_t ADC0_CLKDIV_SEL     : 2;
    __IO uint32_t ADC1_CLKDIV_SEL     : 2;
    uint32_t RESERVED4           : 4;
} DEV_ADC_SDM_CTRL1_Field;
/****DEV_ADCSDM_CTRL1 end****/

/***********************************RSVD_CTRL***********************************/
typedef struct
{

    __IO uint32_t ADC0_RSVD           : 6;
    uint32_t RESERVED0           : 2;
    __IO uint32_t ADC1_RSVD           : 6;
    uint32_t RESERVED1           : 2;
    uint32_t RESERVED2           : 16;
} DEV_ADC_RSVD_CTRL_Field;
/****DEV_ADCRSVD_CTRL end****/

/***********************************VMIC0_CTRL***********************************/
typedef struct
{

    __IO uint32_t VMIC0_EN            : 1;
    __IO uint32_t VMIC0_BYPASS        : 1;
    __IO uint32_t VMIC0_DISCHG        : 1;
    __IO uint32_t VMIC0_REF_SEL       : 1;
    __IO uint32_t VMIC0_VOL           : 4;
    uint32_t RESERVED0           : 24;
} DEV_ADC_VMIC0_CTRL_Field;
/****DEV_ADCVMIC0_CTRL end****/

/***********************************VMIC1_CTRL***********************************/
typedef struct
{

    __IO uint32_t VMIC1_EN            : 1;
    __IO uint32_t VMIC1_BYPASS        : 1;
    __IO uint32_t VMIC1_DISCHG        : 1;
    __IO uint32_t VMIC1_REF_SEL       : 1;
    __IO uint32_t VMIC1_VOL           : 4;
    uint32_t RESERVED0           : 24;
} DEV_ADC_VMIC1_CTRL_Field;
/****DEV_ADCVMIC1_CTRL end****/

/***********************************VMIC_RAMP0***********************************/
typedef struct
{

    __IO uint32_t VMIC0_RAMP_UP_EN    : 1;
    __IO uint32_t VMIC0_RAMP_DN_EN    : 1;
    __IO uint32_t VMIC1_RAMP_UP_EN    : 1;
    __IO uint32_t VMIC1_RAMP_DN_EN    : 1;
    __IO uint32_t FAST_STUP_VMIC      : 1;
    uint32_t RESERVED0           : 11;
    __IO uint32_t RAMP_TIME           : 16;
} DEV_ADC_VMIC_RAMP0_Field;
/****DEV_ADCVMIC_RAMP0 end****/

/***********************************VMIC_RAMP1***********************************/
typedef struct
{

    __IO uint32_t HIGH_NUM            : 16;
    __IO uint32_t TOTAL_NUM           : 16;
} DEV_ADC_VMIC_RAMP1_Field;
/****DEV_ADCVMIC_RAMP1 end****/

/***********************************ANA_PD***********************************/
typedef struct
{

    __IO uint32_t ADC0_OVF            : 1;
    __IO uint32_t ADC1_OVF            : 1;
    uint32_t RESERVED0           : 2;
    __IO uint32_t OUT_ZEROCROSS       : 1;
    uint32_t RESERVED1           : 3;
    uint32_t RESERVED2           : 24;
} DEV_ADC_ANA_PD_Field;
/****DEV_ADCANA_PD end****/

/***********************************DEV_ADC register***********************************/
typedef struct
{

    union
    {
        __IO    uint32_t    CHNn_CFG[4];                             /* 0x0    ADC Channel 0 Configure */
        DEV_ADC_CHNn_CFG_Field    CHNn_CFG_f[4];
    };
    union
    {
        __IO    uint32_t    CFG;                                     /* 0x10    ADC Configure */
        DEV_ADC_CFG_Field    CFG_f;
    };
    union
    {
        __IO    uint32_t    CTL;                                     /* 0x14    ADC Control */
        DEV_ADC_CTL_Field    CTL_f;
    };
    union
    {
        __IO    uint32_t    IE;                                      /* 0x18    ADC Interrupt Enable */
        DEV_ADC_IE_Field    IE_f;
    };
    union
    {
        __IO    uint32_t    PD;                                      /* 0x1c    ADC Interrupt Pending */
        DEV_ADC_PD_Field    PD_f;
    };
    union
    {
        __I     uint32_t    STA;                                     /* 0x20    ADC Status */
        DEV_ADC_STA_Field    STA_f;
    };
    union
    {
        __I     uint32_t    RBUF;                                    /* 0x24    ADCRBUF */
        DEV_ADC_RBUF_Field    RBUF_f;
    };
    uint32_t    RESERVED0[2];
    union
    {
        __IO    uint32_t    GAIN_CFG;                                /* 0x30    ADC Gain Configure */
        DEV_ADC_GAIN_CFG_Field    GAIN_CFG_f;
    };
    union
    {
        __IO    uint32_t    PEAK_AT;                                 /* 0x34    ADC Peak Attack. Time */
        DEV_ADC_PEAK_AT_Field    PEAK_AT_f;
    };
    union
    {
        __IO    uint32_t    PEAK_RT;                                 /* 0x38    ADC Peak Release Time */
        DEV_ADC_PEAK_RT_Field    PEAK_RT_f;
    };
    union
    {
        __IO    uint32_t    GAIN_AT;                                 /* 0x3c    ADC Gain Attack. Time */
        DEV_ADC_GAIN_AT_Field    GAIN_AT_f;
    };
    union
    {
        __IO    uint32_t    GAIN_RT;                                 /* 0x40    ADC Gain Release Time */
        DEV_ADC_GAIN_RT_Field    GAIN_RT_f;
    };
    uint32_t    RESERVED1[3];
    union
    {
        __IO    uint32_t    BIST_EN;                                 /* 0x50    ADC BIST Enable */
        DEV_ADC_BIST_EN_Field    BIST_EN_f;
    };
    union
    {
        __IO    uint32_t    BIST_RM;                                 /* 0x54    ADC BIST Read Margin */
        DEV_ADC_BIST_RM_Field    BIST_RM_f;
    };
    union
    {
        __I     uint32_t    BIST_DONE;                               /* 0x58    ADC BIST done */
        DEV_ADC_BIST_DONE_Field    BIST_DONE_f;
    };
    union
    {
        __I     uint32_t    BIST_FAIL;                               /* 0x5c    ADC BIST fail */
        DEV_ADC_BIST_FAIL_Field    BIST_FAIL_f;
    };
    uint32_t    RESERVED2[8];
    union
    {
        __IO    uint32_t    MIC_CTRL0;                               /* 0x80    ADC Mic Control 0 */
        DEV_ADC_MIC_CTRL0_Field    MIC_CTRL0_f;
    };
    union
    {
        __IO    uint32_t    MIC_CTRL1;                               /* 0x84    ADC Mic Control 1 */
        DEV_ADC_MIC_CTRL1_Field    MIC_CTRL1_f;
    };
    union
    {
        __IO    uint32_t    MIX_CTRL0;                               /* 0x88    ADC Mix Control 0 */
        DEV_ADC_MIX_CTRL0_Field    MIX_CTRL0_f;
    };
    union
    {
        __IO    uint32_t    MIX_CTRL1;                               /* 0x8c    ADC Mix Control 1 */
        DEV_ADC_MIX_CTRL1_Field    MIX_CTRL1_f;
    };
    union
    {
        __IO    uint32_t    SDM_CTRL0;                               /* 0x90    ADC SDM Control 0 */
        DEV_ADC_SDM_CTRL0_Field    SDM_CTRL0_f;
    };
    union
    {
        __IO    uint32_t    SDM_CTRL1;                               /* 0x94    ADC SDM Control 1 */
        DEV_ADC_SDM_CTRL1_Field    SDM_CTRL1_f;
    };
    union
    {
        __IO    uint32_t    RSVD_CTRL;                               /* 0x98    ADC RSVD Control */
        DEV_ADC_RSVD_CTRL_Field    RSVD_CTRL_f;
    };
    union
    {
        __IO    uint32_t    VMIC0_CTRL;                              /* 0x9c    ADC VMIC0 Control */
        DEV_ADC_VMIC0_CTRL_Field    VMIC0_CTRL_f;
    };
    union
    {
        __IO    uint32_t    VMIC1_CTRL;                              /* 0xa0    ADC VMIC1 Control */
        DEV_ADC_VMIC1_CTRL_Field    VMIC1_CTRL_f;
    };
    union
    {
        __IO    uint32_t    VMIC_RAMP0;                              /* 0xa4    ADC VMIC Ramp Control 0 */
        DEV_ADC_VMIC_RAMP0_Field    VMIC_RAMP0_f;
    };
    union
    {
        __IO    uint32_t    VMIC_RAMP1;                              /* 0xa8    ADC VMIC Ramp Control 1 */
        DEV_ADC_VMIC_RAMP1_Field    VMIC_RAMP1_f;
    };
    uint32_t    RESERVED3[17];
    union
    {
        __IO    uint32_t    ANA_PD;                                  /* 0xf0    ADC Analog Status */
        DEV_ADC_ANA_PD_Field    ANA_PD_f;
    };
} DEV_ADC_RegDef_f;
/****DEV_ADC end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
