#ifndef __DEV_CMU_FIELD_H__
#define __DEV_CMU_FIELD_H__

#include "sp2cw3.h"
/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************CLKEN0***********************************/
typedef struct
{

    __IO uint32_t DMA                 : 1;
    __IO uint32_t GPIO                : 1;
    __IO uint32_t EFUSE               : 1;
    __IO uint32_t ASU                 : 1;
    __IO uint32_t EINT                : 1;
    __IO uint32_t TIMER               : 1;
    __IO uint32_t TICK                : 1;
    __IO uint32_t SPI0                : 1;
    __IO uint32_t SPI1                : 1;
    __IO uint32_t UART0               : 1;
    __IO uint32_t UART1               : 1;
    __IO uint32_t UART2               : 1;
    __IO uint32_t I2C0                : 1;
    __IO uint32_t I2C1                : 1;
    __IO uint32_t ASI0                : 1;
    __IO uint32_t ASI1                : 1;
    __IO uint32_t IRRX                : 1;
    __IO uint32_t IRTX                : 1;
    __IO uint32_t PWM                 : 1;
    __IO uint32_t SDC                 : 1;
    __IO uint32_t USB                 : 1;
    uint32_t RESERVED0           : 1;
    __IO uint32_t ADC                 : 1;
    __IO uint32_t DAC                 : 1;
    __IO uint32_t SRC                 : 1;
    __IO uint32_t NPU                 : 1;
    __IO uint32_t UDSP                : 1;
    __IO uint32_t AON                 : 1;
    __IO uint32_t CAMERA              : 1;
    __IO uint32_t UART3               : 1;
    __IO uint32_t MPU                 : 1;
    uint32_t RESERVED1           : 1;
} DEV_CMU_CLKEN0_Field;
/****DEV_CMUCLKEN0 end****/

/***********************************CLKEN1***********************************/
typedef struct
{

    __IO uint32_t CPU                 : 1;
    __IO uint32_t SYS                 : 1;
    __IO uint32_t NORC                : 1;
    __IO uint32_t CACHE               : 1;
    __IO uint32_t RAM0                : 1;
    __IO uint32_t RAM1                : 1;
    __IO uint32_t RAM2                : 1;
    __IO uint32_t RAM3                : 1;
    __IO uint32_t RAM4                : 1;
    __IO uint32_t RAM5                : 1;
    __IO uint32_t RAM6                : 1;
    __IO uint32_t RAM7                : 1;
    __IO uint32_t DEV                 : 1;
    __IO uint32_t HST                 : 1;
    __IO uint32_t MEM                 : 1;
    __IO uint32_t PSRAM               : 1;
    uint32_t RESERVED0           : 16;
} DEV_CMU_CLKEN1_Field;
/****DEV_CMUCLKEN1 end****/

/***********************************SYSCLK***********************************/
typedef struct
{

    __IO uint32_t CORE_SEL            : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t CORE_DIV            : 3;
    uint32_t RESERVED1           : 1;
    __IO uint32_t SYS_DIV             : 3;
    uint32_t RESERVED2           : 21;
} DEV_CMU_SYSCLK_Field;
/****DEV_CMUSYSCLK end****/

/***********************************SPInCLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t DIV                 : 3;
    uint32_t RESERVED1           : 25;
} DEV_CMU_SPInCLK_Field;
/****DEV_CMUSPInCLK end****/

/***********************************I2CnCLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 2;
    uint32_t RESERVED0           : 30;
} DEV_CMU_I2CnCLK_Field;
/****DEV_CMUI2CnCLK end****/

/***********************************UARTnCLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 2;
    uint32_t RESERVED0           : 30;
} DEV_CMU_UARTnCLK_Field;
/****DEV_CMUUARTnCLK end****/

/***********************************NOR0CLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t DIV                 : 3;
    uint32_t RESERVED1           : 25;
} DEV_CMU_NOR0CLK_Field;
/****DEV_CMUNOR0CLK end****/

/***********************************PWMnCLK***********************************/
typedef struct
{

    __IO uint32_t EN                  : 1;
    __IO uint32_t SEL                 : 3;
    __IO uint32_t DIV                 : 13;
    uint32_t RESERVED0           : 15;
} DEV_CMU_PWMnCLK_Field;
/****DEV_CMUPWMnCLK end****/

/***********************************TIMERnCLK***********************************/
typedef struct
{

    __IO uint32_t EN                  : 1;
    __IO uint32_t SEL                 : 3;
    uint32_t RESERVED0           : 28;
} DEV_CMU_TIMERnCLK_Field;
/****DEV_CMUTIMERnCLK end****/

/***********************************ADCCLK***********************************/
typedef struct
{

    __IO uint32_t EN                  : 1;
    __IO uint32_t SEL                 : 3;
    __IO uint32_t DIV                 : 8;
    uint32_t RESERVED0           : 20;
} DEV_CMU_ADCCLK_Field;
/****DEV_CMUADCCLK end****/

/***********************************DACCLK***********************************/
typedef struct
{

    __IO uint32_t EN                  : 1;
    __IO uint32_t SEL                 : 3;
    __IO uint32_t DIG_DIV             : 4;
    __IO uint32_t ANA_DIV             : 2;
    uint32_t RESERVED0           : 2;
    uint32_t RESERVED1           : 20;
} DEV_CMU_DACCLK_Field;
/****DEV_CMUDACCLK end****/

/***********************************ASInCLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t DIV                 : 8;
    uint32_t RESERVED1           : 20;
} DEV_CMU_ASInCLK_Field;
/****DEV_CMUASInCLK end****/

/***********************************IRRXCLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 2;
    uint32_t RESERVED0           : 2;
    __IO uint32_t DIV                 : 8;
    uint32_t RESERVED1           : 20;
} DEV_CMU_IRRXCLK_Field;
/****DEV_CMUIRRXCLK end****/

/***********************************IRTXCLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 2;
    uint32_t RESERVED0           : 2;
    __IO uint32_t DIV                 : 4;
    uint32_t RESERVED1           : 24;
} DEV_CMU_IRTXCLK_Field;
/****DEV_CMUIRTXCLK end****/

/***********************************TICKCLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t DIV                 : 2;
    uint32_t RESERVED1           : 26;
} DEV_CMU_TICKCLK_Field;
/****DEV_CMUTICKCLK end****/

/***********************************SDCCLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t DIV                 : 8;
    uint32_t RESERVED1           : 20;
} DEV_CMU_SDCCLK_Field;
/****DEV_CMUSDCCLK end****/

/***********************************USBCLK***********************************/
typedef struct
{

    __IO uint32_t EN                  : 1;
    uint32_t RESERVED0           : 1;
    __IO uint32_t SEL                 : 2;
    uint32_t RESERVED1           : 1;
} DEV_CMU_USBCLK_Field;
/****DEV_CMUUSBCLK end****/

/***********************************CP2CLK***********************************/
typedef struct
{

    __IO uint32_t EN                  : 1;
    uint32_t RESERVED0           : 1;
    __IO uint32_t SEL                 : 2;
    __IO uint32_t DIV                 : 4;
    uint32_t RESERVED1           : 24;
} DEV_CMU_CP2CLK_Field;
/****DEV_CMUCP2CLK end****/

/***********************************HSCALCLK***********************************/
typedef struct
{

    __IO uint32_t EN                  : 1;
    __IO uint32_t SEL                 : 3;
    uint32_t RESERVED0           : 28;
} DEV_CMU_HSCALCLK_Field;
/****DEV_CMUHSCALCLK end****/

/***********************************DLYCLK***********************************/
typedef struct
{

    __IO uint32_t EN                  : 1;
    __IO uint32_t SEL                 : 2;
    uint32_t RESERVED0           : 29;
} DEV_CMU_DLYCLK_Field;
/****DEV_CMUDLYCLK end****/

/***********************************CAMERACLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t DIV                 : 3;
    uint32_t RESERVED1           : 25;
} DEV_CMU_CAMERACLK_Field;
/****DEV_CMUCAMERACLK end****/

/***********************************UART3CLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 2;
    uint32_t RESERVED0           : 30;
} DEV_CMU_UART3CLK_Field;
/****DEV_CMUUART3CLK end****/

/***********************************PSRAMCLK***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 3;
    uint32_t RESERVED0           : 1;
    __IO uint32_t DIV                 : 3;
    uint32_t RESERVED1           : 25;
} DEV_CMU_PSRAMCLK_Field;
/****DEV_CMUPSRAMCLK end****/

/***********************************CLKDET***********************************/
typedef struct
{

    __IO uint32_t OSC_DEV_DET         : 1;
    __IO uint32_t OSC_XTAL_DET        : 1;
    __IO uint32_t OSC_USB_DET         : 1;
    __IO uint32_t PLL_CORE_DET        : 1;
    __IO uint32_t PLL_AUDIO_DET       : 1;
    __IO uint32_t PLL_USB_DET         : 1;
    __IO uint32_t EXT_CLK_DET         : 1;
    __IO uint32_t EXT_CLK2_DET        : 1;
    uint32_t RESERVED0           : 24;
} DEV_CMU_CLKDET_Field;
/****DEV_CMUCLKDET end****/

/***********************************CLKRDY***********************************/
typedef struct
{

    __I  uint32_t OSC_DEV_RDY         : 1;
    __I  uint32_t OSC_XTAL_RDY        : 1;
    __I  uint32_t OSC_USB_RDY         : 1;
    __I  uint32_t PLL_CORE_RDY        : 1;
    __I  uint32_t PLL_AUDIO_RDY       : 1;
    __I  uint32_t PLL_USB_RDY         : 1;
    __I  uint32_t EXT_CLK_RDY         : 1;
    __I  uint32_t EXT_CLK2_RDY        : 1;
    uint32_t RESERVED0           : 24;
} DEV_CMU_CLKRDY_Field;
/****DEV_CMUCLKRDY end****/

/***********************************DBGCTL***********************************/
typedef struct
{

    __IO uint32_t SEL                 : 7;
    uint32_t RESERVED0           : 1;
    __IO uint32_t DIV                 : 3;
    uint32_t RESERVED1           : 21;
} DEV_CMU_DBGCTL_Field;
/****DEV_CMUDBGCTL end****/

/***********************************TESTCTL***********************************/
typedef struct
{

    __IO uint32_t OSC_ADC             : 1;
    __IO uint32_t OSC_DEV             : 1;
    __IO uint32_t OSC_XTAL            : 1;
    __IO uint32_t OSC_USB             : 1;
    __IO uint32_t PLL_CORE            : 1;
    __IO uint32_t PLL_AUDIO           : 1;
    __IO uint32_t PLL_USB             : 1;
    __IO uint32_t USB_SOF             : 1;
    __I  uint32_t P_TEST              : 1;
    uint32_t RESERVED0           : 23;
} DEV_CMU_TESTCTL_Field;
/****DEV_CMUTESTCTL end****/

/***********************************DEV_CMU register***********************************/
typedef struct
{

    union
    {
        __IO    uint32_t    CLKEN0;                                  /* 0x0    Clock Enable */
        DEV_CMU_CLKEN0_Field    CLKEN0_f;
    };
    union
    {
        __IO    uint32_t    CLKEN1;                                  /* 0x4    Clock Enable */
        DEV_CMU_CLKEN1_Field    CLKEN1_f;
    };
    uint32_t    RESERVED0[2];
    union
    {
        __IO    uint32_t    SYSCLK;                                  /* 0x10    System Clock */
        DEV_CMU_SYSCLK_Field    SYSCLK_f;
    };
    uint32_t    RESERVED1[3];
    union
    {
        __IO    uint32_t    SPInCLK[2];                              /* 0x20    SPI0 Clock */
        DEV_CMU_SPInCLK_Field    SPInCLK_f[2];
    };
    union
    {
        __IO    uint32_t    I2CnCLK[2];                              /* 0x28    I2C0 Clock */
        DEV_CMU_I2CnCLK_Field    I2CnCLK_f[2];
    };
    union
    {
        __IO    uint32_t    UARTnCLK[3];                             /* 0x30    UART0 Clock */
        DEV_CMU_UARTnCLK_Field    UARTnCLK_f[3];
    };
    union
    {
        __IO    uint32_t    NOR0CLK;                                 /* 0x3c    NOR0 Clock */
        DEV_CMU_NOR0CLK_Field    NOR0CLK_f;
    };
    union
    {
        __IO    uint32_t    PWMnCLK[8];                              /* 0x40    PWM0 Clock */
        DEV_CMU_PWMnCLK_Field    PWMnCLK_f[8];
    };
    union
    {
        __IO    uint32_t    TIMERnCLK[4];                            /* 0x60    Timer0 Clock */
        DEV_CMU_TIMERnCLK_Field    TIMERnCLK_f[4];
    };
    union
    {
        __IO    uint32_t    ADCCLK;                                  /* 0x70    Audio ADC Clock */
        DEV_CMU_ADCCLK_Field    ADCCLK_f;
    };
    union
    {
        __IO    uint32_t    DACCLK;                                  /* 0x74    Audio DAC Clock */
        DEV_CMU_DACCLK_Field    DACCLK_f;
    };
    union
    {
        __IO    uint32_t    ASInCLK[2];                              /* 0x78    Audio Serial Interface0 Clock */
        DEV_CMU_ASInCLK_Field    ASInCLK_f[2];
    };
    union
    {
        __IO    uint32_t    IRRXCLK;                                 /* 0x80    IRRX Clock */
        DEV_CMU_IRRXCLK_Field    IRRXCLK_f;
    };
    union
    {
        __IO    uint32_t    IRTXCLK;                                 /* 0x84    IRTX Clock */
        DEV_CMU_IRTXCLK_Field    IRTXCLK_f;
    };
    union
    {
        __IO    uint32_t    TICKCLK;                                 /* 0x88    TICK Clock */
        DEV_CMU_TICKCLK_Field    TICKCLK_f;
    };
    union
    {
        __IO    uint32_t    SDCCLK;                                  /* 0x8c    SD Controller Clock */
        DEV_CMU_SDCCLK_Field    SDCCLK_f;
    };
    union
    {
        __IO    uint32_t    USBCLK;                                  /* 0x90    USB Controller Clock */
        DEV_CMU_USBCLK_Field    USBCLK_f;
    };
    union
    {
        __IO    uint32_t    CP2CLK;                                  /* 0x94    Charge Pump Clock 2 */
        DEV_CMU_CP2CLK_Field    CP2CLK_f;
    };
    union
    {
        __IO    uint32_t    HSCALCLK;                                /* 0x98    Headset Calibration Clock */
        DEV_CMU_HSCALCLK_Field    HSCALCLK_f;
    };
    union
    {
        __IO    uint32_t    DLYCLK;                                  /* 0x9c    DMIC Delay Clock */
        DEV_CMU_DLYCLK_Field    DLYCLK_f;
    };
    union
    {
        __IO    uint32_t    CAMERACLK;                               /* 0xa0    CAMERA Clock */
        DEV_CMU_CAMERACLK_Field    CAMERACLK_f;
    };
    union
    {
        __IO    uint32_t    UART3CLK;                                /* 0xa4    UART3 Clock */
        DEV_CMU_UART3CLK_Field    UART3CLK_f;
    };
    union
    {
        __IO    uint32_t    PSRAMCLK;                                /* 0xa8    PSRAM Clock */
        DEV_CMU_PSRAMCLK_Field    PSRAMCLK_f;
    };
    uint32_t    RESERVED2[17];
    union
    {
        __IO    uint32_t    CLKDET;                                  /* 0xf0    Clock Detect */
        DEV_CMU_CLKDET_Field    CLKDET_f;
    };
    union
    {
        __I     uint32_t    CLKRDY;                                  /* 0xf4    Clock Ready */
        DEV_CMU_CLKRDY_Field    CLKRDY_f;
    };
    union
    {
        __IO    uint32_t    DBGCTL;                                  /* 0xf8    Debug Control */
        DEV_CMU_DBGCTL_Field    DBGCTL_f;
    };
    union
    {
        __IO    uint32_t    TESTCTL;                                 /* 0xfc    Test Control */
        DEV_CMU_TESTCTL_Field    TESTCTL_f;
    };
} DEV_CMU_RegDef_f;
/****DEV_CMU end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
