#ifndef __DEV_UDSP_FIELD_H__
#define __DEV_UDSP_FIELD_H__

#include "sp2cw3.h"
/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************uDSP_CHNn_SLA***********************************/
typedef struct
{
    __IO uint32_t SRC_LOWER_ADDR      : 32;
} DEV_UDSP_uDSP_CHNn_SLA_Field;
/****DEV_UDSPuDSP_CHNn_SLA end****/

/***********************************uDSP_CHNn_SUA***********************************/
typedef struct
{
    __IO uint32_t SRC_UPPER_ADDR      : 32;
} DEV_UDSP_uDSP_CHNn_SUA_Field;
/****DEV_UDSPuDSP_CHNn_SUA end****/

/***********************************uDSP_CHNn_SCA***********************************/
typedef struct
{
    __IO uint32_t SRC_CURRENT_ADDR    : 32;
} DEV_UDSP_uDSP_CHNn_SCA_Field;
/****DEV_UDSPuDSP_CHNn_SCA end****/

/***********************************uDSP_CHNn_SMF***********************************/
typedef struct
{
    __IO uint32_t SRC_DATA_LENGTH     : 12;
    __IO uint32_t SRC_DATA_WIDTH      : 2;
    __IO uint32_t SRC_DATA_FORMAT     : 1;
    __IO uint32_t SRC_DATA_TYPE       : 1;
    __IO uint32_t SRC_OFFSET_ADDR     : 16;
} DEV_UDSP_uDSP_CHNn_SMF_Field;
/****DEV_UDSPuDSP_CHNn_SMF end****/

/***********************************uDSP_CHNn_DLA***********************************/
typedef struct
{
    __IO uint32_t DST_LOWER_ADDR      : 32;
} DEV_UDSP_uDSP_CHNn_DLA_Field;
/****DEV_UDSPuDSP_CHNn_DLA end****/

/***********************************uDSP_CHNn_DUA***********************************/
typedef struct
{
    __IO uint32_t DST_UPPER_ADDR      : 32;
} DEV_UDSP_uDSP_CHNn_DUA_Field;
/****DEV_UDSPuDSP_CHNn_DUA end****/

/***********************************uDSP_CHNn_DCA***********************************/
typedef struct
{
    __IO uint32_t DST_CURRENT_ADDR    : 32;
} DEV_UDSP_uDSP_CHNn_DCA_Field;
/****DEV_UDSPuDSP_CHNn_DCA end****/

/***********************************uDSP_CHNn_DMF***********************************/
typedef struct
{
    __IO uint32_t DST_DATA_LENGTH     : 12;
    __IO uint32_t DST_DATA_WIDTH      : 2;
    uint32_t RESERVED0           : 1;
    __IO uint32_t DST_DATA_TYPE       : 1;
    __IO uint32_t DST_OFFSET_ADDR     : 16;
} DEV_UDSP_uDSP_CHNn_DMF_Field;
/****DEV_UDSPuDSP_CHNn_DMF end****/

/***********************************uDSP_CHNn_LMF0***********************************/
typedef struct
{
    __IO uint32_t SMA_WR_BUF0_SEL     : 1;
    __IO uint32_t SMA_RD_BUF0_SEL     : 1;
    uint32_t RESERVED0           : 2;
    __IO uint32_t SMA_BUF0_WSA        : 4;
    __IO uint32_t SMA_BUF0_RSA        : 4;
    uint32_t RESERVED1           : 4;
    __IO uint32_t SMA_WR_BUF1_SEL     : 1;
    __IO uint32_t SMA_RD_BUF1_SEL     : 1;
    uint32_t RESERVED2           : 2;
    __IO uint32_t SMA_BUF1_WSA        : 4;
    __IO uint32_t SMA_BUF1_RSA        : 4;
    __IO uint32_t FIR_BUF1_WSA        : 4;
} DEV_UDSP_uDSP_CHNn_LMF0_Field;
/****DEV_UDSPuDSP_CHNn_LMF0 end****/

/***********************************uDSP_CHNn_LMF1***********************************/
typedef struct
{
    __IO uint32_t ATAN_BUF0_WSA       : 2;
    __IO uint32_t ATAN_BUF0_RSA       : 2;
    __IO uint32_t ABS2_BUF0_WSA       : 2;
    __IO uint32_t ABS2_BUF0_RSA       : 2;
    __IO uint32_t SQRT_BUF0_WSA       : 2;
    __IO uint32_t SQRT_BUF0_RSA       : 2;
    __IO uint32_t FBK_BUF0_WSA        : 2;
    __IO uint32_t FBK_BUF0_RSA        : 2;
    __IO uint32_t LOG_BUF0_WSA        : 2;
    __IO uint32_t LOG_BUF0_RSA        : 2;
    __IO uint32_t MAC_BUF0_WSA        : 4;
    __IO uint32_t MAC_BUF0_RSA        : 4;
    __IO uint32_t FIR_BUF0_WSA        : 2;
    __IO uint32_t FIR_BUF0_RSA        : 2;
} DEV_UDSP_uDSP_CHNn_LMF1_Field;
/****DEV_UDSPuDSP_CHNn_LMF1 end****/

/***********************************uDSP_CHNn_LMF2***********************************/
typedef struct
{
    __IO uint32_t WIN_BUF1_RSA        : 8;
    __IO uint32_t COS_BUF1_RSA        : 8;
    __IO uint32_t MUL_BUF1_RSA        : 8;
    __IO uint32_t SQRT_BUF1_RSA       : 8;
} DEV_UDSP_uDSP_CHNn_LMF2_Field;
/****DEV_UDSPuDSP_CHNn_LMF2 end****/

/***********************************uDSP_CHNn_LMF3***********************************/
typedef struct
{
    __IO uint32_t FBK_BUF1_RSA        : 8;
    __IO uint32_t MAC_BUF1_RSA        : 8;
    __IO uint32_t FIR_BUF1_RSA        : 8;
    __IO uint32_t DIV_BUF1_RSA        : 8;
} DEV_UDSP_uDSP_CHNn_LMF3_Field;
/****DEV_UDSPuDSP_CHNn_LMF3 end****/

/***********************************uDSP_CHNn_LMF4***********************************/
typedef struct
{
    __IO uint32_t COS_SHIFT_SEL       : 4;
    __IO uint32_t FFT_SHIFT_SEL       : 4;
    __IO uint32_t MUL_SHIFT_SEL       : 4;
    __IO uint32_t IFFT_SHIFT_SEL      : 4;
    __IO uint32_t SQRT_SHIFT_SEL      : 4;
    __IO uint32_t MAC_SHIFT_SEL       : 4;
    __IO uint32_t FIR_SHIFT_SEL       : 4;
    __IO uint32_t DIV_SHIFT_SEL       : 4;
} DEV_UDSP_uDSP_CHNn_LMF4_Field;
/****DEV_UDSPuDSP_CHNn_LMF4 end****/

/***********************************uDSP_CHNn_CFG0***********************************/
typedef struct
{
    __IO uint32_t SMR                 : 1;
    __IO uint32_t PRE                 : 1;
    __IO uint32_t WIN                 : 1;
    __IO uint32_t COS                 : 1;
    __IO uint32_t FFT                 : 1;
    __IO uint32_t MUL                 : 1;
    __IO uint32_t IFFT                : 1;
    __IO uint32_t ATAN                : 1;
    __IO uint32_t ABS2                : 1;
    __IO uint32_t SQRT                : 1;
    __IO uint32_t FBK                 : 1;
    __IO uint32_t LOG                 : 1;
    __IO uint32_t MAC                 : 1;
    __IO uint32_t FIR                 : 1;
    __IO uint32_t DIV                 : 1;
    __IO uint32_t SMW                 : 1;
    uint32_t RESERVED0           : 4;
    __IO uint32_t FFT_POINT           : 3;
    __IO uint32_t LOG_CAL             : 1;
    __IO uint32_t LOG_8BIT            : 1;
    __IO uint32_t BUF_SWAP            : 1;
    uint32_t RESERVED1           : 6;
} DEV_UDSP_uDSP_CHNn_CFG0_Field;
/****DEV_UDSPuDSP_CHNn_CFG0 end****/

/***********************************uDSP_CHNn_CFG1***********************************/
typedef struct
{
    __IO uint32_t BANK_NUM            : 16;
    __IO uint32_t MFCC_NUM            : 16;
} DEV_UDSP_uDSP_CHNn_CFG1_Field;
/****DEV_UDSPuDSP_CHNn_CFG1 end****/

/***********************************uDSP_EN***********************************/
typedef struct
{
    __IO uint32_t CHN_EN              : 8;
    uint32_t RESERVED0           : 8;
    __O  uint32_t CHN_EN_WE           : 8;
    uint32_t RESERVED1           : 8;
} DEV_UDSP_uDSP_EN_Field;
/****DEV_UDSPuDSP_EN end****/

/***********************************uDSP_IE***********************************/
typedef struct
{
    __IO uint32_t END                 : 8;
    uint32_t RESERVED0           : 8;
    __IO uint32_t FFT_BIT31_OF        : 1;
    __IO uint32_t FFT_BIT32_OF        : 1;
    uint32_t RESERVED1           : 14;
} DEV_UDSP_uDSP_IE_Field;
/****DEV_UDSPuDSP_IE end****/

/***********************************uDSP_PD***********************************/
typedef struct
{
    __IO uint32_t END                 : 8;
    uint32_t RESERVED0           : 8;
    __IO uint32_t FFT_BIT31_OF        : 1;
    __IO uint32_t FFT_BIT32_OF        : 1;
    uint32_t RESERVED1           : 14;
} DEV_UDSP_uDSP_PD_Field;
/****DEV_UDSPuDSP_PD end****/

/***********************************uDSP_BIST_CFG***********************************/
typedef struct
{
    __IO uint32_t BUF0_RM             : 4;
    __IO uint32_t BUF0_RME            : 1;
    __IO uint32_t BUF0_BIST_LS        : 1;
    uint32_t RESERVED0           : 2;
    __IO uint32_t BUF1_RM             : 4;
    __IO uint32_t BUF1_RME            : 1;
    __IO uint32_t BUF1_BIST_LS        : 1;
    uint32_t RESERVED1           : 2;
    uint32_t RESERVED2           : 16;
} DEV_UDSP_uDSP_BIST_CFG_Field;
/****DEV_UDSPuDSP_BIST_CFG end****/

/***********************************uDSP_BIST_EN***********************************/
typedef struct
{
    __IO uint32_t BUF0_BIST_EN        : 1;
    __IO uint32_t BUF1_BIST_EN        : 1;
    uint32_t RESERVED0           : 30;
} DEV_UDSP_uDSP_BIST_EN_Field;
/****DEV_UDSPuDSP_BIST_EN end****/

/***********************************uDSP_BIST_DONE***********************************/
typedef struct
{
    __I  uint32_t BUF0_BIST_DONE      : 1;
    __I  uint32_t BUF1_BIST_DONE      : 1;
    uint32_t RESERVED0           : 30;
} DEV_UDSP_uDSP_BIST_DONE_Field;
/****DEV_UDSPuDSP_BIST_DONE end****/

/***********************************uDSP_BIST_FAIL***********************************/
typedef struct
{
    __I  uint32_t BUF0_BIST_FAIL      : 1;
    __I  uint32_t BUF1_BIST_FAIL      : 1;
    uint32_t RESERVED0           : 30;
} DEV_UDSP_uDSP_BIST_FAIL_Field;
/****DEV_UDSPuDSP_BIST_FAIL end****/

/***********************************uDSP_CHN register***********************************/
typedef struct
{
    union
    {
        __IO    uint32_t    SLA;                                     /* 0x0    uDSP Channel 0 Source Lower ADDR */
        DEV_UDSP_uDSP_CHNn_SLA_Field    SLA_f;
    };
    union
    {
        __IO    uint32_t    SUA;                                     /* 0x4    uDSP Channel 0 Source Upper ADDR */
        DEV_UDSP_uDSP_CHNn_SUA_Field    SUA_f;
    };
    union
    {
        __IO    uint32_t    SCA;                                     /* 0x8    uDSP Channel 0 Source Current ADDR */
        DEV_UDSP_uDSP_CHNn_SCA_Field    SCA_f;
    };
    union
    {
        __IO    uint32_t    SMF;                                     /* 0xc    uDSP Channel 0 Source Memory Format */
        DEV_UDSP_uDSP_CHNn_SMF_Field    SMF_f;
    };
    union
    {
        __IO    uint32_t    DLA;                                     /* 0x10    uDSP Channel 0 Destination Lower ADDR */
        DEV_UDSP_uDSP_CHNn_DLA_Field    DLA_f;
    };
    union
    {
        __IO    uint32_t    DUA;                                     /* 0x14    uDSP Channel 0 Destination Upper ADDR */
        DEV_UDSP_uDSP_CHNn_DUA_Field    DUA_f;
    };
    union
    {
        __IO    uint32_t    DCA;                                     /* 0x18    uDSP Channel 0 Destination Current ADDR */
        DEV_UDSP_uDSP_CHNn_DCA_Field    DCA_f;
    };
    union
    {
        __IO    uint32_t    DMF;                                     /* 0x1c    uDSP Channel 0 Destination Memory Format */
        DEV_UDSP_uDSP_CHNn_DMF_Field    DMF_f;
    };
    union
    {
        __IO    uint32_t    LMF0;                                    /* 0x20    uDSP Channel 0 Local Memory Format 0 */
        DEV_UDSP_uDSP_CHNn_LMF0_Field    LMF0_f;
    };
    union
    {
        __IO    uint32_t    LMF1;                                    /* 0x24    uDSP Channel 0 Local Memory Format 1 */
        DEV_UDSP_uDSP_CHNn_LMF1_Field    LMF1_f;
    };
    union
    {
        __IO    uint32_t    LMF2;                                    /* 0x28    uDSP Channel 0 Local Memory Format 2 */
        DEV_UDSP_uDSP_CHNn_LMF2_Field    LMF2_f;
    };
    union
    {
        __IO    uint32_t    LMF3;                                    /* 0x2c    uDSP Channel 0 Local Memory Format 3 */
        DEV_UDSP_uDSP_CHNn_LMF3_Field    LMF3_f;
    };
    union
    {
        __IO    uint32_t    LMF4;                                    /* 0x30    uDSP Channel 0 Local Memory Format 4 */
        DEV_UDSP_uDSP_CHNn_LMF4_Field    LMF4_f;
    };
    uint32_t    RESERVED0[19];
    union
    {
        __IO    uint32_t    CFG0;                                    /* 0x80    uDSP Channel 0 Configure 0 */
        DEV_UDSP_uDSP_CHNn_CFG0_Field    CFG0_f;
    };
    union
    {
        __IO    uint32_t    CFG1;                                    /* 0x84    uDSP Channel 0 Configure 1 */
        DEV_UDSP_uDSP_CHNn_CFG1_Field    CFG1_f;
    };
    uint32_t    RESERVED1[30];
} uDSP_CHN_RegDef_f;
/****uDSP_CHN end****/

/***********************************DEV_UDSP register***********************************/
typedef struct
{
    union
    {
        uDSP_CHN_RegDef_f    CHN[8];                                  /* 0x0    uDSP Channel 0 Source Lower ADDR */
    };
    uint32_t    RESERVED0[512];
    union
    {
        __IO    uint32_t    EN;                                      /* 0x1000    uDSP Channel 1 Source Upper ADDR */
        DEV_UDSP_uDSP_EN_Field    EN_f;
    };
    union
    {
        __IO    uint32_t    IE;                                      /* 0x1004    uDSP Channel 1 Source Memory Format */
        DEV_UDSP_uDSP_IE_Field    IE_f;
    };
    union
    {
        __IO    uint32_t    PD;                                      /* 0x1008    uDSP Channel 1 Destination Upper ADDR */
        DEV_UDSP_uDSP_PD_Field    PD_f;
    };
    uint32_t    RESERVED1[1021];
    union
    {
        __IO    uint32_t    BIST_CFG;                                /* 0x2000    uDSP Channel 1 Destination Memory Format */
        DEV_UDSP_uDSP_BIST_CFG_Field    BIST_CFG_f;
    };
    union
    {
        __IO    uint32_t    BIST_EN;                                 /* 0x2004    uDSP Channel 1 Local Memory Format 1 */
        DEV_UDSP_uDSP_BIST_EN_Field    BIST_EN_f;
    };
    union
    {
        __I     uint32_t    BIST_DONE;                               /* 0x2008    uDSP Channel 1 Local Memory Format 3 */
        DEV_UDSP_uDSP_BIST_DONE_Field    BIST_DONE_f;
    };
    union
    {
        __I     uint32_t    BIST_FAIL;                               /* 0x200c    uDSP Channel 1 Configure 0 */
        DEV_UDSP_uDSP_BIST_FAIL_Field    BIST_FAIL_f;
    };
} DEV_UDSP_RegDef_f;
/****DEV_UDSP end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
