#ifndef __DEV_DAC_H__
#define __DEV_DAC_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************CHNL_IIRn_B0***********************************/
#define DEV_DAC_CHNL_IIRn_B0_MASK                               (0xffffffffUL<<0)
/****CHNL_IIRn_B0 end****/


/***********************************CHNL_IIRn_B1***********************************/
#define DEV_DAC_CHNL_IIRn_B1_MASK                               (0xffffffffUL<<0)
/****CHNL_IIRn_B1 end****/


/***********************************CHNL_IIRn_B2***********************************/
#define DEV_DAC_CHNL_IIRn_B2_MASK                               (0xffffffffUL<<0)
/****CHNL_IIRn_B2 end****/


/***********************************CHNL_IIRn_A1***********************************/
#define DEV_DAC_CHNL_IIRn_A1_MASK                               (0xffffffffUL<<0)
/****CHNL_IIRn_A1 end****/


/***********************************CHNL_IIRn_A2***********************************/
#define DEV_DAC_CHNL_IIRn_A2_MASK                               (0xffffffffUL<<0)
/****CHNL_IIRn_A2 end****/


/***********************************CHNL_IIR7_B0***********************************/
#define DEV_DAC_CHNL_IIR7_B0_MASK                               (0xffffffffUL<<0)
/****CHNL_IIR7_B0 end****/


/***********************************CHNL_IIR7_B1***********************************/
#define DEV_DAC_CHNL_IIR7_B1_MASK                               (0xffffffffUL<<0)
/****CHNL_IIR7_B1 end****/


/***********************************CHNL_IIR7_B2***********************************/
#define DEV_DAC_CHNL_IIR7_B2_MASK                               (0xffffffffUL<<0)
/****CHNL_IIR7_B2 end****/


/***********************************CHNL_IIR7_A1***********************************/
#define DEV_DAC_CHNL_IIR7_A1_MASK                               (0xffffffffUL<<0)
/****CHNL_IIR7_A1 end****/


/***********************************CHNL_IIR7_A2***********************************/
#define DEV_DAC_CHNL_IIR7_A2_MASK                               (0xffffffffUL<<0)
/****CHNL_IIR7_A2 end****/


/***********************************CHNR_IIRn_B0***********************************/
#define DEV_DAC_CHNR_IIRn_B0_MASK                               (0xffffffffUL<<0)
/****CHNR_IIRn_B0 end****/


/***********************************CHNR_IIRn_B1***********************************/
#define DEV_DAC_CHNR_IIRn_B1_MASK                               (0xffffffffUL<<0)
/****CHNR_IIRn_B1 end****/


/***********************************CHNR_IIRn_B2***********************************/
#define DEV_DAC_CHNR_IIRn_B2_MASK                               (0xffffffffUL<<0)
/****CHNR_IIRn_B2 end****/


/***********************************CHNR_IIRn_A1***********************************/
#define DEV_DAC_CHNR_IIRn_A1_MASK                               (0xffffffffUL<<0)
/****CHNR_IIRn_A1 end****/


/***********************************CHNR_IIRn_A2***********************************/
#define DEV_DAC_CHNR_IIRn_A2_MASK                               (0xffffffffUL<<0)
/****CHNR_IIRn_A2 end****/


/***********************************CHNR_IIR7_B0***********************************/
#define DEV_DAC_CHNR_IIR7_B0_MASK                               (0xffffffffUL<<0)
/****CHNR_IIR7_B0 end****/


/***********************************CHNR_IIR7_B1***********************************/
#define DEV_DAC_CHNR_IIR7_B1_MASK                               (0xffffffffUL<<0)
/****CHNR_IIR7_B1 end****/


/***********************************CHNR_IIR7_B2***********************************/
#define DEV_DAC_CHNR_IIR7_B2_MASK                               (0xffffffffUL<<0)
/****CHNR_IIR7_B2 end****/


/***********************************CHNR_IIR7_A1***********************************/
#define DEV_DAC_CHNR_IIR7_A1_MASK                               (0xffffffffUL<<0)
/****CHNR_IIR7_A1 end****/


/***********************************CHNR_IIR7_A2***********************************/
#define DEV_DAC_CHNR_IIR7_A2_MASK                               (0xffffffffUL<<0)
/****CHNR_IIR7_A2 end****/


/***********************************DRC_LMTH***********************************/
#define DEV_DAC_DRC_LMTH_MASK                                   (0xffffffffUL<<0)
/****DRC_LMTH end****/


/***********************************DRC_SLOP***********************************/
#define DEV_DAC_DRC_SLOP_MASK                                   (0xffffffffUL<<0)
/****DRC_SLOP end****/


/***********************************DRC_PEAK_AT***********************************/
#define DEV_DAC_DRC_PEAK_AT_ATTACK_TIME_MASK                    (0xffffffffUL<<0)
/****DRC_PEAK_AT end****/


/***********************************DRC_PEAK_RT***********************************/
#define DEV_DAC_DRC_PEAK_RT_RELEASE_TIME_MASK                   (0xffffffffUL<<0)
/****DRC_PEAK_RT end****/


/***********************************DRC_GAIN_AT***********************************/
#define DEV_DAC_DRC_GAIN_AT_ATTACK_TIME_MASK                    (0xffffffffUL<<0)
/****DRC_GAIN_AT end****/


/***********************************DRC_GAIN_RT***********************************/
#define DEV_DAC_DRC_GAIN_RT_RELEASE_TIME_MASK                   (0xffffffffUL<<0)
/****DRC_GAIN_RT end****/


/***********************************DSD_COE_B1***********************************/
#define DEV_DAC_DSD_COE_B1_MASK                                 (0xffffffffUL<<0)
/****DSD_COE_B1 end****/


/***********************************DSD_COE_B2***********************************/
#define DEV_DAC_DSD_COE_B2_MASK                                 (0xffffffffUL<<0)
/****DSD_COE_B2 end****/


/***********************************DSD_COE_A1***********************************/
#define DEV_DAC_DSD_COE_A1_MASK                                 (0xffffffffUL<<0)
/****DSD_COE_A1 end****/


/***********************************DSD_COE_A2***********************************/
#define DEV_DAC_DSD_COE_A2_MASK                                 (0xffffffffUL<<0)
/****DSD_COE_A2 end****/


/***********************************DSD_COE_A3***********************************/
#define DEV_DAC_DSD_COE_A3_MASK                                 (0xffffffffUL<<0)
/****DSD_COE_A3 end****/


/***********************************DAC_CFG0***********************************/
#define DEV_DAC_CFG0_CHNR_IIR_SEL_DISABLE                       (0x0UL<<24)
#define DEV_DAC_CFG0_CHNR_IIR_SEL_ENABLE                        (0x1UL<<24)
#define DEV_DAC_CFG0_CHNR_IIR_SEL_MASK                          (0xffUL<<24)
#define DEV_DAC_CFG0_CHNL_IIR_SEL_DISABLE                       (0x0UL<<16)
#define DEV_DAC_CFG0_CHNL_IIR_SEL_ENABLE                        (0x1UL<<16)
#define DEV_DAC_CFG0_CHNL_IIR_SEL_MASK                          (0xffUL<<16)
#define DEV_DAC_CFG0_DACR_INVERSE_NORMAL                        (0x0UL<<15)
#define DEV_DAC_CFG0_DACR_INVERSE_INVERSE                       (0x1UL<<15)
#define DEV_DAC_CFG0_DACR_INVERSE_MASK                          (0x1UL<<15)
#define DEV_DAC_CFG0_DACL_INVERSE_NORMAL                        (0x0UL<<14)
#define DEV_DAC_CFG0_DACL_INVERSE_INVERSE                       (0x1UL<<14)
#define DEV_DAC_CFG0_DACL_INVERSE_MASK                          (0x1UL<<14)
#define DEV_DAC_CFG0_HEMP_TH_MASK                               (0x3fUL<<8)
#define DEV_DAC_CFG0_DITHER_SEL_LEFTSHIFT23BIT                  (0x0UL<<6)
#define DEV_DAC_CFG0_DITHER_SEL_LEFTSHIFT22BIT                  (0x1UL<<6)
#define DEV_DAC_CFG0_DITHER_SEL_LEFTSHIFT21BIT                  (0x2UL<<6)
#define DEV_DAC_CFG0_DITHER_SEL_LEFTSHIFT20BIT                  (0x3UL<<6)
#define DEV_DAC_CFG0_DITHER_SEL_MASK                            (0x3UL<<6)
#define DEV_DAC_CFG0_DITHER_EN_DISABLE                          (0x0UL<<5)
#define DEV_DAC_CFG0_DITHER_EN_ENABLE                           (0x1UL<<5)
#define DEV_DAC_CFG0_DITHER_EN_MASK                             (0x1UL<<5)
#define DEV_DAC_CFG0_SRC_SEL_AHBINTERFACE                       (0x0UL<<4)
#define DEV_DAC_CFG0_SRC_SEL_SRCINTERFACE                       (0x1UL<<4)
#define DEV_DAC_CFG0_SRC_SEL_MASK                               (0x1UL<<4)
#define DEV_DAC_CFG0_IIR_SR_IN_1FS                              (0x0UL<<2)
#define DEV_DAC_CFG0_IIR_SR_IN_2FS                              (0x1UL<<2)
#define DEV_DAC_CFG0_IIR_SR_IN_4FS                              (0x2UL<<2)
#define DEV_DAC_CFG0_IIR_SR_IN_8FS                              (0x3UL<<2)
#define DEV_DAC_CFG0_IIR_SR_IN_MASK                             (0x3UL<<2)
#define DEV_DAC_CFG0_DMIC_SRC_DACFIFO                           (0x0UL<<1)
#define DEV_DAC_CFG0_DMIC_SRC_DMIC                              (0x1UL<<1)
#define DEV_DAC_CFG0_DMIC_SRC_MASK                              (0x1UL<<1)
#define DEV_DAC_CFG0_SIN_SRC_DACFIFO                            (0x0UL<<0)
#define DEV_DAC_CFG0_SIN_SRC_SINTABLE                           (0x1UL<<0)
#define DEV_DAC_CFG0_SIN_SRC_MASK                               (0x1UL<<0)
/****DAC_CFG0 end****/


/***********************************DAC_CFG1***********************************/
#define DEV_DAC_CFG1_DAC_VOL_R_MUTE                             (0x0UL<<24)
#define DEV_DAC_CFG1_DAC_VOL_R_40DB                             (0x1UL<<24)
#define DEV_DAC_CFG1_DAC_VOL_R_39DB                             (0x2UL<<24)
#define DEV_DAC_CFG1_DAC_VOL_R_MASK                             (0x3fUL<<24)
#define DEV_DAC_CFG1_DAC_VOL_L_MUTE                             (0x0UL<<16)
#define DEV_DAC_CFG1_DAC_VOL_L_40DB                             (0x1UL<<16)
#define DEV_DAC_CFG1_DAC_VOL_L_39DB                             (0x2UL<<16)
#define DEV_DAC_CFG1_DAC_VOL_L_MASK                             (0x3fUL<<16)
#define DEV_DAC_CFG1_DBG_CHN_SEL_LEFTCHANNEL                    (0x0UL<<14)
#define DEV_DAC_CFG1_DBG_CHN_SEL_RIGHTCHANNEL                   (0x1UL<<14)
#define DEV_DAC_CFG1_DBG_CHN_SEL_MASK                           (0x1UL<<14)
#define DEV_DAC_CFG1_DBG_OUT_EN_DISABLE                         (0x0UL<<13)
#define DEV_DAC_CFG1_DBG_OUT_EN_ENABLE                          (0x1UL<<13)
#define DEV_DAC_CFG1_DBG_OUT_EN_MASK                            (0x1UL<<13)
#define DEV_DAC_CFG1_DBG_IN_EN_DISABLE                          (0x0UL<<12)
#define DEV_DAC_CFG1_DBG_IN_EN_ENABLE                           (0x1UL<<12)
#define DEV_DAC_CFG1_DBG_IN_EN_MASK                             (0x1UL<<12)
#define DEV_DAC_CFG1_DACR_MIX_GAIN_1                            (0x0UL<<10)
#define DEV_DAC_CFG1_DACR_MIX_GAIN_1_2                          (0x1UL<<10)
#define DEV_DAC_CFG1_DACR_MIX_GAIN_1_4                          (0x2UL<<10)
#define DEV_DAC_CFG1_DACR_MIX_GAIN_MASK                         (0x3UL<<10)
#define DEV_DAC_CFG1_DACL_MIX_GAIN_1                            (0x0UL<<8)
#define DEV_DAC_CFG1_DACL_MIX_GAIN_1_2                          (0x1UL<<8)
#define DEV_DAC_CFG1_DACL_MIX_GAIN_1_4                          (0x2UL<<8)
#define DEV_DAC_CFG1_DACL_MIX_GAIN_MASK                         (0x3UL<<8)
#define DEV_DAC_CFG1_DACR_MIX_SOURCE_DISABLE                    (0x0UL<<4)
#define DEV_DAC_CFG1_DACR_MIX_SOURCE_ENABLE                     (0x1UL<<4)
#define DEV_DAC_CFG1_DACR_MIX_SOURCE_MASK                       (0xfUL<<4)
#define DEV_DAC_CFG1_DACL_MIX_SOURCE_DISABLE                    (0x0UL<<0)
#define DEV_DAC_CFG1_DACL_MIX_SOURCE_ENABLE                     (0x1UL<<0)
#define DEV_DAC_CFG1_DACL_MIX_SOURCE_MASK                       (0xfUL<<0)
/****DAC_CFG1 end****/


/***********************************DAC_CTL***********************************/
#define DEV_DAC_CTL_DSD_EN_DISABLE                              (0x0UL<<6)
#define DEV_DAC_CTL_DSD_EN_ENABLE                               (0x1UL<<6)
#define DEV_DAC_CTL_DSD_EN_MASK                                 (0x1UL<<6)
#define DEV_DAC_CTL_DRC_EN_DISABLE                              (0x0UL<<5)
#define DEV_DAC_CTL_DRC_EN_ENABLE                               (0x1UL<<5)
#define DEV_DAC_CTL_DRC_EN_MASK                                 (0x1UL<<5)
#define DEV_DAC_CTL_ANC_EN_DISABLE                              (0x0UL<<4)
#define DEV_DAC_CTL_ANC_EN_ENABLE                               (0x1UL<<4)
#define DEV_DAC_CTL_ANC_EN_MASK                                 (0x1UL<<4)
#define DEV_DAC_CTL_EQ_EN_DISABLE                               (0x0UL<<3)
#define DEV_DAC_CTL_EQ_EN_ENABLE                                (0x1UL<<3)
#define DEV_DAC_CTL_EQ_EN_MASK                                  (0x1UL<<3)
#define DEV_DAC_CTL_TX_FIFO_RST_TXFIFOWORK                      (0x0UL<<2)
#define DEV_DAC_CTL_TX_FIFO_RST_TXFIFORESET                     (0x1UL<<2)
#define DEV_DAC_CTL_TX_FIFO_RST_MASK                            (0x1UL<<2)
#define DEV_DAC_CTL_DMA_EN_DISABLE                              (0x0UL<<1)
#define DEV_DAC_CTL_DMA_EN_ENABLE                               (0x1UL<<1)
#define DEV_DAC_CTL_DMA_EN_MASK                                 (0x1UL<<1)
#define DEV_DAC_CTL_TX_EN_DISABLE                               (0x0UL<<0)
#define DEV_DAC_CTL_TX_EN_ENABLE                                (0x1UL<<0)
#define DEV_DAC_CTL_TX_EN_MASK                                  (0x1UL<<0)
/****DAC_CTL end****/


/***********************************DAC_IE***********************************/
#define DEV_DAC_IE_TX_FIFO_UF                                   (0x1UL<<2)
#define DEV_DAC_IE_TX_FIFO_OF                                   (0x1UL<<1)
#define DEV_DAC_IE_TX_IRQ                                       (0x1UL<<0)
/****DAC_IE end****/


/***********************************DAC_PD***********************************/
#define DEV_DAC_PD_TX_FIFO_UF                                   (0x1UL<<2)
#define DEV_DAC_PD_TX_FIFO_OF                                   (0x1UL<<1)
#define DEV_DAC_PD_TX_IRQ                                       (0x1UL<<0)
/****DAC_PD end****/


/***********************************DAC_STA***********************************/
#define DEV_DAC_STA_TX_FIFO_FULL                                (0x1UL<<11)
#define DEV_DAC_STA_TX_FIFO_HFUL                                (0x1UL<<10)
#define DEV_DAC_STA_TX_FIFO_EMPT                                (0x1UL<<9)
#define DEV_DAC_STA_TX_FIFO_HEMP                                (0x1UL<<8)
#define DEV_DAC_STA_TX_FIFO_WLVL_MASK                           (0x3fUL<<0)
/****DAC_STA end****/


/***********************************DAC_TBUF***********************************/
#define DEV_DAC_TBUF_MASK                                       (0xffffffffUL<<0)
/****DAC_TBUF end****/


/***********************************DAC_CFG2***********************************/
#define DEV_DAC_CFG2_DSD_VOL_R_MUTE                             (0x0UL<<24)
#define DEV_DAC_CFG2_DSD_VOL_R_40DB                             (0x1UL<<24)
#define DEV_DAC_CFG2_DSD_VOL_R_39DB                             (0x2UL<<24)
#define DEV_DAC_CFG2_DSD_VOL_R_MASK                             (0x3fUL<<24)
#define DEV_DAC_CFG2_DSD_VOL_L_MUTE                             (0x0UL<<16)
#define DEV_DAC_CFG2_DSD_VOL_L_40DB                             (0x1UL<<16)
#define DEV_DAC_CFG2_DSD_VOL_L_39DB                             (0x2UL<<16)
#define DEV_DAC_CFG2_DSD_VOL_L_MASK                             (0x3fUL<<16)
#define DEV_DAC_CFG2_DAC_FMT_USEHI_MASK                         (0x1UL<<13)
#define DEV_DAC_CFG2_DAC_FMT_16BIT_MASK                         (0x1UL<<12)
#define DEV_DAC_CFG2_DSD_FMT_START_MASK                         (0x3UL<<10)
#define DEV_DAC_CFG2_DSD_FMT_BO_MASK                            (0x1UL<<9)
#define DEV_DAC_CFG2_DSD_FMT_16BIT_MASK                         (0x1UL<<8)
#define DEV_DAC_CFG2_DCB_EN_DISABLE                             (0x0UL<<5)
#define DEV_DAC_CFG2_DCB_EN_ENABLE                              (0x1UL<<5)
#define DEV_DAC_CFG2_DCB_EN_MASK                                (0x1UL<<5)
#define DEV_DAC_CFG2_MONO_EN_STEREO                             (0x0UL<<4)
#define DEV_DAC_CFG2_MONO_EN_MONO                               (0x1UL<<4)
#define DEV_DAC_CFG2_MONO_EN_MASK                               (0x1UL<<4)
#define DEV_DAC_CFG2_ANA_CLK_DIV_1                              (0x0UL<<2)
#define DEV_DAC_CFG2_ANA_CLK_DIV_2                              (0x1UL<<2)
#define DEV_DAC_CFG2_ANA_CLK_DIV_4                              (0x2UL<<2)
#define DEV_DAC_CFG2_ANA_CLK_DIV_8                              (0x3UL<<2)
#define DEV_DAC_CFG2_ANA_CLK_DIV_MASK                           (0x3UL<<2)
#define DEV_DAC_CFG2_CIC_SR_OUT_128FS                           (0x0UL<<0)
#define DEV_DAC_CFG2_CIC_SR_OUT_64FS                            (0x1UL<<0)
#define DEV_DAC_CFG2_CIC_SR_OUT_32FS                            (0x2UL<<0)
#define DEV_DAC_CFG2_CIC_SR_OUT_16FS                            (0x3UL<<0)
#define DEV_DAC_CFG2_CIC_SR_OUT_MASK                            (0x3UL<<0)
/****DAC_CFG2 end****/


/***********************************DAC_DCB***********************************/
#define DEV_DAC_DCB_MASK                                        (0xffffffUL<<0)
/****DAC_DCB end****/


/***********************************DAC_BIST_RM***********************************/
#define DEV_DAC_BIST_RM_RAM_RM_MASK                             (0xfUL<<0)
/****DAC_BIST_RM end****/


/***********************************DAC_BIST_EN***********************************/
#define DEV_DAC_BIST_EN_RAM_LS_DISABLE                          (0x0UL<<2)
#define DEV_DAC_BIST_EN_RAM_LS_ENABLE                           (0x1UL<<2)
#define DEV_DAC_BIST_EN_RAM_LS_MASK                             (0x1UL<<2)
#define DEV_DAC_BIST_EN_RAM_RME_DISABLE                         (0x0UL<<1)
#define DEV_DAC_BIST_EN_RAM_RME_ENABLE                          (0x1UL<<1)
#define DEV_DAC_BIST_EN_RAM_RME_MASK                            (0x1UL<<1)
#define DEV_DAC_BIST_EN_RAM_EN_DISABLE                          (0x0UL<<0)
#define DEV_DAC_BIST_EN_RAM_EN_ENABLE                           (0x1UL<<0)
#define DEV_DAC_BIST_EN_RAM_EN_MASK                             (0x1UL<<0)
/****DAC_BIST_EN end****/


/***********************************DAC_BIST_DONE***********************************/
#define DEV_DAC_BIST_DONE_RAM_DONE                              (0x1UL<<0)
/****DAC_BIST_DONE end****/


/***********************************DAC_BIST_FAIL***********************************/
#define DEV_DAC_BIST_FAIL_RAM_FAIL                              (0x1UL<<0)
/****DAC_BIST_FAIL end****/


/***********************************DAC_DA_CTL***********************************/
#define DEV_DAC_DA_CTL_DAC_RSVD_11_MASK                         (0x3fUL<<18)
#define DEV_DAC_DA_CTL_LO_VCMI_CHOP_DISABLE                     (0x0UL<<17)
#define DEV_DAC_DA_CTL_LO_VCMI_CHOP_ENABLE                      (0x1UL<<17)
#define DEV_DAC_DA_CTL_LO_VCMI_CHOP_MASK                        (0x1UL<<17)
#define DEV_DAC_DA_CTL_LO_VCMI_BYP_DONOTBYPASS                  (0x0UL<<16)
#define DEV_DAC_DA_CTL_LO_VCMI_BYP_BYPASS                       (0x1UL<<16)
#define DEV_DAC_DA_CTL_LO_VCMI_BYP_MASK                         (0x1UL<<16)
#define DEV_DAC_DA_CTL_DAC_CLK_DLY_1N                           (0x0UL<<12)
#define DEV_DAC_DA_CTL_DAC_CLK_DLY_2N                           (0x1UL<<12)
#define DEV_DAC_DA_CTL_DAC_CLK_DLY_3N                           (0x2UL<<12)
#define DEV_DAC_DA_CTL_DAC_CLK_DLY_5N                           (0x3UL<<12)
#define DEV_DAC_DA_CTL_DAC_CLK_DLY_MASK                         (0x3UL<<12)
#define DEV_DAC_DA_CTL_DAC_CLK_INVSEL_DISABLE                   (0x0UL<<11)
#define DEV_DAC_DA_CTL_DAC_CLK_INVSEL_ENABLE                    (0x1UL<<11)
#define DEV_DAC_DA_CTL_DAC_CLK_INVSEL_MASK                      (0x1UL<<11)
#define DEV_DAC_DA_CTL_DAC_OPFB_PD                              (0x1UL<<10)
#define DEV_DAC_DA_CTL_DAC_NONOV_MASK                           (0x3UL<<8)
#define DEV_DAC_DA_CTL_DAC_IBIAS_CTRL_MASK                      (0x3UL<<6)
#define DEV_DAC_DA_CTL_DAC_CHOP_DIV_MASK                        (0x3UL<<4)
#define DEV_DAC_DA_CTL_DAC_GBW_SEL_DISABLE                      (0x0UL<<3)
#define DEV_DAC_DA_CTL_DAC_GBW_SEL_ENABLE                       (0x1UL<<3)
#define DEV_DAC_DA_CTL_DAC_GBW_SEL_MASK                         (0x1UL<<3)
#define DEV_DAC_DA_CTL_DAC_CHOP_EN_DISABLE                      (0x0UL<<2)
#define DEV_DAC_DA_CTL_DAC_CHOP_EN_ENABLE                       (0x1UL<<2)
#define DEV_DAC_DA_CTL_DAC_CHOP_EN_MASK                         (0x1UL<<2)
#define DEV_DAC_DA_CTL_DAC1_EN_DISABLE                          (0x0UL<<1)
#define DEV_DAC_DA_CTL_DAC1_EN_ENABLE                           (0x1UL<<1)
#define DEV_DAC_DA_CTL_DAC1_EN_MASK                             (0x1UL<<1)
#define DEV_DAC_DA_CTL_DAC0_EN_DISABLE                          (0x0UL<<0)
#define DEV_DAC_DA_CTL_DAC0_EN_ENABLE                           (0x1UL<<0)
#define DEV_DAC_DA_CTL_DAC0_EN_MASK                             (0x1UL<<0)
/****DAC_DA_CTL end****/


/***********************************DAC_CP_CTL***********************************/
#define DEV_DAC_CP_CTL_CP_CLK_DLY_1N                            (0x0UL<<8)
#define DEV_DAC_CP_CTL_CP_CLK_DLY_2N                            (0x1UL<<8)
#define DEV_DAC_CP_CTL_CP_CLK_DLY_3N                            (0x2UL<<8)
#define DEV_DAC_CP_CTL_CP_CLK_DLY_5N                            (0x3UL<<8)
#define DEV_DAC_CP_CTL_CP_CLK_DLY_MASK                          (0x3UL<<8)
#define DEV_DAC_CP_CTL_CP_CLK_NONOV_1N                          (0x0UL<<6)
#define DEV_DAC_CP_CTL_CP_CLK_NONOV_2N                          (0x1UL<<6)
#define DEV_DAC_CP_CTL_CP_CLK_NONOV_3N                          (0x2UL<<6)
#define DEV_DAC_CP_CTL_CP_CLK_NONOV_5N                          (0x3UL<<6)
#define DEV_DAC_CP_CTL_CP_CLK_NONOV_MASK                        (0x3UL<<6)
#define DEV_DAC_CP_CTL_CP_CLK_DIV_8                             (0x0UL<<4)
#define DEV_DAC_CP_CTL_CP_CLK_DIV_16                            (0x1UL<<4)
#define DEV_DAC_CP_CTL_CP_CLK_DIV_32                            (0x2UL<<4)
#define DEV_DAC_CP_CTL_CP_CLK_DIV_64                            (0x3UL<<4)
#define DEV_DAC_CP_CTL_CP_CLK_DIV_MASK                          (0x3UL<<4)
#define DEV_DAC_CP_CTL_CP_CLK_INV_SEL_DISABLE                   (0x0UL<<3)
#define DEV_DAC_CP_CTL_CP_CLK_INV_SEL_ENABLE                    (0x1UL<<3)
#define DEV_DAC_CP_CTL_CP_CLK_INV_SEL_MASK                      (0x1UL<<3)
#define DEV_DAC_CP_CTL_CP_CLK_SEL_DISABLE                       (0x0UL<<2)
#define DEV_DAC_CP_CTL_CP_CLK_SEL_ENABLE                        (0x1UL<<2)
#define DEV_DAC_CP_CTL_CP_CLK_SEL_MASK                          (0x1UL<<2)
#define DEV_DAC_CP_CTL_CP_HS_EN_DISABLE                         (0x0UL<<1)
#define DEV_DAC_CP_CTL_CP_HS_EN_ENABLE                          (0x1UL<<1)
#define DEV_DAC_CP_CTL_CP_HS_EN_MASK                            (0x1UL<<1)
#define DEV_DAC_CP_CTL_CP_EN_DISABLE                            (0x0UL<<0)
#define DEV_DAC_CP_CTL_CP_EN_ENABLE                             (0x1UL<<0)
#define DEV_DAC_CP_CTL_CP_EN_MASK                               (0x1UL<<0)
/****DAC_CP_CTL end****/


/***********************************DAC_HP_CTL0***********************************/
#define DEV_DAC_HP_CTL0_GMIC1_S78_EN_DISABLE                    (0x0UL<<25)
#define DEV_DAC_HP_CTL0_GMIC1_S78_EN_ENABLE                     (0x1UL<<25)
#define DEV_DAC_HP_CTL0_GMIC1_S78_EN_MASK                       (0x1UL<<25)
#define DEV_DAC_HP_CTL0_GMIC0_S78_EN_DISABLE                    (0x0UL<<24)
#define DEV_DAC_HP_CTL0_GMIC0_S78_EN_ENABLE                     (0x1UL<<24)
#define DEV_DAC_HP_CTL0_GMIC0_S78_EN_MASK                       (0x1UL<<24)
#define DEV_DAC_HP_CTL0_HPFBSW1_EN_DISABLE                      (0x0UL<<23)
#define DEV_DAC_HP_CTL0_HPFBSW1_EN_ENABLE                       (0x1UL<<23)
#define DEV_DAC_HP_CTL0_HPFBSW1_EN_MASK                         (0x1UL<<23)
#define DEV_DAC_HP_CTL0_HPFBSW0_EN_DISABLE                      (0x0UL<<22)
#define DEV_DAC_HP_CTL0_HPFBSW0_EN_ENABLE                       (0x1UL<<22)
#define DEV_DAC_HP_CTL0_HPFBSW0_EN_MASK                         (0x1UL<<22)
#define DEV_DAC_HP_CTL0_GMIC1_EN_DISABLE                        (0x0UL<<21)
#define DEV_DAC_HP_CTL0_GMIC1_EN_ENABLE                         (0x1UL<<21)
#define DEV_DAC_HP_CTL0_GMIC1_EN_MASK                           (0x1UL<<21)
#define DEV_DAC_HP_CTL0_GMIC0_EN_DISABLE                        (0x0UL<<20)
#define DEV_DAC_HP_CTL0_GMIC0_EN_ENABLE                         (0x1UL<<20)
#define DEV_DAC_HP_CTL0_GMIC0_EN_MASK                           (0x1UL<<20)
#define DEV_DAC_HP_CTL0_HSCAL1_EN_DISABLE                       (0x0UL<<19)
#define DEV_DAC_HP_CTL0_HSCAL1_EN_ENABLE                        (0x1UL<<19)
#define DEV_DAC_HP_CTL0_HSCAL1_EN_MASK                          (0x1UL<<19)
#define DEV_DAC_HP_CTL0_HSCAL0_EN_DISABLE                       (0x0UL<<18)
#define DEV_DAC_HP_CTL0_HSCAL0_EN_ENABLE                        (0x1UL<<18)
#define DEV_DAC_HP_CTL0_HSCAL0_EN_MASK                          (0x1UL<<18)
#define DEV_DAC_HP_CTL0_HSPA_IBIAS_CTL_5U                       (0x0UL<<16)
#define DEV_DAC_HP_CTL0_HSPA_IBIAS_CTL_10U                      (0x1UL<<16)
#define DEV_DAC_HP_CTL0_HSPA_IBIAS_CTL_15U                      (0x2UL<<16)
#define DEV_DAC_HP_CTL0_HSPA_IBIAS_CTL_2_5U                     (0x3UL<<16)
#define DEV_DAC_HP_CTL0_HSPA_IBIAS_CTL_MASK                     (0x3UL<<16)
#define DEV_DAC_HP_CTL0_HSPA_IBGM3_CTL_1U                       (0x0UL<<14)
#define DEV_DAC_HP_CTL0_HSPA_IBGM3_CTL_2U                       (0x1UL<<14)
#define DEV_DAC_HP_CTL0_HSPA_IBGM3_CTL_3U                       (0x2UL<<14)
#define DEV_DAC_HP_CTL0_HSPA_IBGM3_CTL_5U                       (0x3UL<<14)
#define DEV_DAC_HP_CTL0_HSPA_IBGM3_CTL_MASK                     (0x3UL<<14)
#define DEV_DAC_HP_CTL0_HSPA_IBGM2_CTL_1U                       (0x0UL<<12)
#define DEV_DAC_HP_CTL0_HSPA_IBGM2_CTL_2U                       (0x1UL<<12)
#define DEV_DAC_HP_CTL0_HSPA_IBGM2_CTL_3U                       (0x2UL<<12)
#define DEV_DAC_HP_CTL0_HSPA_IBGM2_CTL_5U                       (0x3UL<<12)
#define DEV_DAC_HP_CTL0_HSPA_IBGM2_CTL_MASK                     (0x3UL<<12)
#define DEV_DAC_HP_CTL0_HSPA_IBGM1_CTL_1U                       (0x0UL<<10)
#define DEV_DAC_HP_CTL0_HSPA_IBGM1_CTL_2U                       (0x1UL<<10)
#define DEV_DAC_HP_CTL0_HSPA_IBGM1_CTL_3U                       (0x2UL<<10)
#define DEV_DAC_HP_CTL0_HSPA_IBGM1_CTL_5U                       (0x3UL<<10)
#define DEV_DAC_HP_CTL0_HSPA_IBGM1_CTL_MASK                     (0x3UL<<10)
#define DEV_DAC_HP_CTL0_HSPA1_MIX1_EN_DISABLE                   (0x0UL<<9)
#define DEV_DAC_HP_CTL0_HSPA1_MIX1_EN_USEMIX1                   (0x1UL<<9)
#define DEV_DAC_HP_CTL0_HSPA1_MIX1_EN_MASK                      (0x1UL<<9)
#define DEV_DAC_HP_CTL0_HSPA1_MIX0_EN_DISABLE                   (0x0UL<<8)
#define DEV_DAC_HP_CTL0_HSPA1_MIX0_EN_USEMIX0                   (0x1UL<<8)
#define DEV_DAC_HP_CTL0_HSPA1_MIX0_EN_MASK                      (0x1UL<<8)
#define DEV_DAC_HP_CTL0_HSPA1_DAC1_EN_DISABLE                   (0x0UL<<7)
#define DEV_DAC_HP_CTL0_HSPA1_DAC1_EN_USEDAC                    (0x1UL<<7)
#define DEV_DAC_HP_CTL0_HSPA1_DAC1_EN_MASK                      (0x1UL<<7)
#define DEV_DAC_HP_CTL0_HSPA1_DAC0_EN_DISABLE                   (0x0UL<<6)
#define DEV_DAC_HP_CTL0_HSPA1_DAC0_EN_USEDAC                    (0x1UL<<6)
#define DEV_DAC_HP_CTL0_HSPA1_DAC0_EN_MASK                      (0x1UL<<6)
#define DEV_DAC_HP_CTL0_HSPA0_MIX1_EN_DISABLE                   (0x0UL<<5)
#define DEV_DAC_HP_CTL0_HSPA0_MIX1_EN_USEMIX1                   (0x1UL<<5)
#define DEV_DAC_HP_CTL0_HSPA0_MIX1_EN_MASK                      (0x1UL<<5)
#define DEV_DAC_HP_CTL0_HSPA0_MIX0_EN_DISABLE                   (0x0UL<<4)
#define DEV_DAC_HP_CTL0_HSPA0_MIX0_EN_USEMIX0                   (0x1UL<<4)
#define DEV_DAC_HP_CTL0_HSPA0_MIX0_EN_MASK                      (0x1UL<<4)
#define DEV_DAC_HP_CTL0_HSPA0_DAC1_EN_DISABLE                   (0x0UL<<3)
#define DEV_DAC_HP_CTL0_HSPA0_DAC1_EN_ENABLE                    (0x1UL<<3)
#define DEV_DAC_HP_CTL0_HSPA0_DAC1_EN_MASK                      (0x1UL<<3)
#define DEV_DAC_HP_CTL0_HSPA0_DAC0_EN_DISABLE                   (0x0UL<<2)
#define DEV_DAC_HP_CTL0_HSPA0_DAC0_EN_ENABLE                    (0x1UL<<2)
#define DEV_DAC_HP_CTL0_HSPA0_DAC0_EN_MASK                      (0x1UL<<2)
#define DEV_DAC_HP_CTL0_HSPA1_EN_DISABLE                        (0x0UL<<1)
#define DEV_DAC_HP_CTL0_HSPA1_EN_ENABLE                         (0x1UL<<1)
#define DEV_DAC_HP_CTL0_HSPA1_EN_MASK                           (0x1UL<<1)
#define DEV_DAC_HP_CTL0_HSPA0_EN_DISABLE                        (0x0UL<<0)
#define DEV_DAC_HP_CTL0_HSPA0_EN_ENABLE                         (0x1UL<<0)
#define DEV_DAC_HP_CTL0_HSPA0_EN_MASK                           (0x1UL<<0)
/****DAC_HP_CTL0 end****/


/***********************************DAC_LO_CTL0***********************************/
#define DEV_DAC_LO_CTL0_LO_IBIAS_CTL_5U                         (0x0UL<<17)
#define DEV_DAC_LO_CTL0_LO_IBIAS_CTL_10U                        (0x1UL<<17)
#define DEV_DAC_LO_CTL0_LO_IBIAS_CTL_15U                        (0x2UL<<17)
#define DEV_DAC_LO_CTL0_LO_IBIAS_CTL_2_5U                       (0x3UL<<17)
#define DEV_DAC_LO_CTL0_LO_IBIAS_CTL_MASK                       (0x3UL<<17)
#define DEV_DAC_LO_CTL0_LO_PD_STUP_ENABLESTARTUP                (0x0UL<<16)
#define DEV_DAC_LO_CTL0_LO_PD_STUP_POWERDOWNSTARTUP             (0x1UL<<16)
#define DEV_DAC_LO_CTL0_LO_PD_STUP_MASK                         (0x1UL<<16)
#define DEV_DAC_LO_CTL0_LO_VCMSTUP_CTL_MASK                     (0x3UL<<14)
#define DEV_DAC_LO_CTL0_LO_FASTSTUP_DISABLEFASTSTARTUP          (0x0UL<<13)
#define DEV_DAC_LO_CTL0_LO_FASTSTUP_ENABLEFASTSTARTUP           (0x1UL<<13)
#define DEV_DAC_LO_CTL0_LO_FASTSTUP_MASK                        (0x1UL<<13)
#define DEV_DAC_LO_CTL0_LO_CHOP_EN_DISABLE                      (0x0UL<<12)
#define DEV_DAC_LO_CTL0_LO_CHOP_EN_ENABLE                       (0x1UL<<12)
#define DEV_DAC_LO_CTL0_LO_CHOP_EN_MASK                         (0x1UL<<12)
#define DEV_DAC_LO_CTL0_LO1_MIX1_EN_DISABLE                     (0x0UL<<11)
#define DEV_DAC_LO_CTL0_LO1_MIX1_EN_USEMIX1                     (0x1UL<<11)
#define DEV_DAC_LO_CTL0_LO1_MIX1_EN_MASK                        (0x1UL<<11)
#define DEV_DAC_LO_CTL0_LO1_MIX0_EN_DISABLE                     (0x0UL<<10)
#define DEV_DAC_LO_CTL0_LO1_MIX0_EN_USEMIX0                     (0x1UL<<10)
#define DEV_DAC_LO_CTL0_LO1_MIX0_EN_MASK                        (0x1UL<<10)
#define DEV_DAC_LO_CTL0_LO1_DAC1_EN_DISABLE                     (0x0UL<<9)
#define DEV_DAC_LO_CTL0_LO1_DAC1_EN_USEDAC                      (0x1UL<<9)
#define DEV_DAC_LO_CTL0_LO1_DAC1_EN_MASK                        (0x1UL<<9)
#define DEV_DAC_LO_CTL0_LO1_DAC0_EN_DISABLE                     (0x0UL<<8)
#define DEV_DAC_LO_CTL0_LO1_DAC0_EN_USEDAC                      (0x1UL<<8)
#define DEV_DAC_LO_CTL0_LO1_DAC0_EN_MASK                        (0x1UL<<8)
#define DEV_DAC_LO_CTL0_LO0_MIX1_EN_DISABLE                     (0x0UL<<7)
#define DEV_DAC_LO_CTL0_LO0_MIX1_EN_USEMIX1                     (0x1UL<<7)
#define DEV_DAC_LO_CTL0_LO0_MIX1_EN_MASK                        (0x1UL<<7)
#define DEV_DAC_LO_CTL0_LO0_MIX0_EN_DISABLE                     (0x0UL<<6)
#define DEV_DAC_LO_CTL0_LO0_MIX0_EN_USEMIX0                     (0x1UL<<6)
#define DEV_DAC_LO_CTL0_LO0_MIX0_EN_MASK                        (0x1UL<<6)
#define DEV_DAC_LO_CTL0_LO0_DAC1_EN_DISABLE                     (0x0UL<<5)
#define DEV_DAC_LO_CTL0_LO0_DAC1_EN_USEDAC                      (0x1UL<<5)
#define DEV_DAC_LO_CTL0_LO0_DAC1_EN_MASK                        (0x1UL<<5)
#define DEV_DAC_LO_CTL0_LO0_DAC0_EN_DISABLE                     (0x0UL<<4)
#define DEV_DAC_LO_CTL0_LO0_DAC0_EN_USEDAC                      (0x1UL<<4)
#define DEV_DAC_LO_CTL0_LO0_DAC0_EN_MASK                        (0x1UL<<4)
#define DEV_DAC_LO_CTL0_LO1_DIFF_EN_DISABLE                     (0x0UL<<3)
#define DEV_DAC_LO_CTL0_LO1_DIFF_EN_ENABLE                      (0x1UL<<3)
#define DEV_DAC_LO_CTL0_LO1_DIFF_EN_MASK                        (0x1UL<<3)
#define DEV_DAC_LO_CTL0_LO1_EN_DISABLE                          (0x0UL<<2)
#define DEV_DAC_LO_CTL0_LO1_EN_ENABLE                           (0x1UL<<2)
#define DEV_DAC_LO_CTL0_LO1_EN_MASK                             (0x1UL<<2)
#define DEV_DAC_LO_CTL0_LO0_DIFF_EN_DISABLE                     (0x0UL<<1)
#define DEV_DAC_LO_CTL0_LO0_DIFF_EN_ENABLE                      (0x1UL<<1)
#define DEV_DAC_LO_CTL0_LO0_DIFF_EN_MASK                        (0x1UL<<1)
#define DEV_DAC_LO_CTL0_LO0_EN_DISABLE                          (0x0UL<<0)
#define DEV_DAC_LO_CTL0_LO0_EN_ENABLE                           (0x1UL<<0)
#define DEV_DAC_LO_CTL0_LO0_EN_MASK                             (0x1UL<<0)
/****DAC_LO_CTL0 end****/


/***********************************DAC_LO_CTL1***********************************/
#define DEV_DAC_LO_CTL1_RAMP_TIME_MASK                          (0xffffUL<<16)
#define DEV_DAC_LO_CTL1_LO1_RAMP_DN_EN_DISABLE                  (0x0UL<<3)
#define DEV_DAC_LO_CTL1_LO1_RAMP_DN_EN_ENABLE                   (0x1UL<<3)
#define DEV_DAC_LO_CTL1_LO1_RAMP_DN_EN_MASK                     (0x1UL<<3)
#define DEV_DAC_LO_CTL1_LO1_RAMP_UP_EN_DISABLE                  (0x0UL<<2)
#define DEV_DAC_LO_CTL1_LO1_RAMP_UP_EN_ENABLE                   (0x1UL<<2)
#define DEV_DAC_LO_CTL1_LO1_RAMP_UP_EN_MASK                     (0x1UL<<2)
#define DEV_DAC_LO_CTL1_LO0_RAMP_DN_EN_DISABLE                  (0x0UL<<1)
#define DEV_DAC_LO_CTL1_LO0_RAMP_DN_EN_ENABLE                   (0x1UL<<1)
#define DEV_DAC_LO_CTL1_LO0_RAMP_DN_EN_MASK                     (0x1UL<<1)
#define DEV_DAC_LO_CTL1_LO0_RAMP_UP_EN_DISABLE                  (0x0UL<<0)
#define DEV_DAC_LO_CTL1_LO0_RAMP_UP_EN_ENABLE                   (0x1UL<<0)
#define DEV_DAC_LO_CTL1_LO0_RAMP_UP_EN_MASK                     (0x1UL<<0)
/****DAC_LO_CTL1 end****/


/***********************************DAC_LO_CTL2***********************************/
#define DEV_DAC_LO_CTL2_TOTAL_NUM_MASK                          (0xffffUL<<16)
#define DEV_DAC_LO_CTL2_HIGH_NUM_MASK                           (0xffffUL<<0)
/****DAC_LO_CTL2 end****/


/***********************************DAC_HP_CTL1***********************************/
#define DEV_DAC_HP_CTL1_DIV_CNT_MASK                            (0xffUL<<0)
/****DAC_HP_CTL1 end****/


/***********************************CHNL_IIR register***********************************/
typedef struct
{
    __IO    uint32_t    B0;                                      /* 0x0    Left. Channel IIR0 Coefficient B0 */
    __IO    uint32_t    B1;                                      /* 0x4    Left. Channel IIR0 Coefficient B1 */
    __IO    uint32_t    B2;                                      /* 0x8    Left. Channel IIR0 Coefficient B2 */
    __IO    uint32_t    A1;                                      /* 0xc    Left. Channel IIR0 Coefficient A1 */
    __IO    uint32_t    A2;                                      /* 0x10    Left. Channel IIR0 Coefficient A2 */
    uint32_t    RESERVED0[59];
} CHNL_IIR_RegDef;
/****CHNL_IIR end****/

/***********************************CHNR_IIR register***********************************/
typedef struct
{
    __IO    uint32_t    B0;                                      /* 0x800    Left. Channel IIR2 Coefficient B0 */
    __IO    uint32_t    B1;                                      /* 0x804    Left. Channel IIR2 Coefficient B1 */
    __IO    uint32_t    B2;                                      /* 0x808    Left. Channel IIR2 Coefficient B2 */
    __IO    uint32_t    A1;                                      /* 0x80c    Left. Channel IIR2 Coefficient A1 */
    __IO    uint32_t    A2;                                      /* 0x810    Left. Channel IIR2 Coefficient A2 */
    uint32_t    RESERVED0[59];
} CHNR_IIR_RegDef;
/****CHNR_IIR end****/

/***********************************DEV_DAC register***********************************/
typedef struct
{
    CHNL_IIR_RegDef    CHNL_IIR[7];                             /* 0x0    Left. Channel IIR0 Coefficient B0 */
    __IO    uint32_t    CHNL_IIR7_B0;                            /* 0x700    Left. Channel IIR2 Coefficient B2 */
    __IO    uint32_t    CHNL_IIR7_B1;                            /* 0x704    Left. Channel IIR2 Coefficient A2 */
    __IO    uint32_t    CHNL_IIR7_B2;                            /* 0x708    Left. Channel IIR3 Coefficient B1 */
    __IO    uint32_t    CHNL_IIR7_A1;                            /* 0x70c    Left. Channel IIR3 Coefficient A1 */
    __IO    uint32_t    CHNL_IIR7_A2;                            /* 0x710    Left. Channel IIR3 Coefficient A2 */
    uint32_t    RESERVED0[59];
    CHNR_IIR_RegDef    CHNR_IIR[7];                             /* 0x800    Left. Channel IIR4 Coefficient B0 */
    __IO    uint32_t    CHNR_IIR7_B0;                            /* 0xf00    Left. Channel IIR5 Coefficient B2 */
    __IO    uint32_t    CHNR_IIR7_B1;                            /* 0xf04    Left. Channel IIR5 Coefficient A1 */
    __IO    uint32_t    CHNR_IIR7_B2;                            /* 0xf08    Left. Channel IIR5 Coefficient A2 */
    __IO    uint32_t    CHNR_IIR7_A1;                            /* 0xf0c    Left. Channel IIR6 Coefficient B0 */
    __IO    uint32_t    CHNR_IIR7_A2;                            /* 0xf10    Left. Channel IIR6 Coefficient B1 */
    uint32_t    RESERVED1[28];
    __IO    uint32_t    DRC_LMTH;                                /* 0xf84    Left. Channel IIR6 Coefficient B2 */
    __IO    uint32_t    DRC_SLOP;                                /* 0xf88    Left. Channel IIR6 Coefficient A1 */
    __IO    uint32_t    DRC_PEAK_AT;                             /* 0xf8c    Left. Channel IIR6 Coefficient A2 */
    __IO    uint32_t    DRC_PEAK_RT;                             /* 0xf90    Left. Channel IIR7 Coefficient B0 */
    __IO    uint32_t    DRC_GAIN_AT;                             /* 0xf94    Left. Channel IIR7 Coefficient B1 */
    __IO    uint32_t    DRC_GAIN_RT;                             /* 0xf98    Left. Channel IIR7 Coefficient B2 */
    uint32_t    RESERVED2[9];
    __IO    uint32_t    DSD_COE_B1;                              /* 0xfc0    Left. Channel IIR7 Coefficient A1 */
    __IO    uint32_t    DSD_COE_B2;                              /* 0xfc4    Left. Channel IIR7 Coefficient A2 */
    __IO    uint32_t    DSD_COE_A1;                              /* 0xfc8    Right Channel IIR0 Coefficient B0 */
    __IO    uint32_t    DSD_COE_A2;                              /* 0xfcc    Right Channel IIR0 Coefficient B1 */
    __IO    uint32_t    DSD_COE_A3;                              /* 0xfd0    Right Channel IIR0 Coefficient B2 */
    uint32_t    RESERVED3[11];
    __IO    uint32_t    CFG0;                                    /* 0x1000    Right Channel IIR0 Coefficient A1 */
    __IO    uint32_t    CFG1;                                    /* 0x1004    Right Channel IIR0 Coefficient A2 */
    __IO    uint32_t    CTL;                                     /* 0x1008    Right Channel IIR1 Coefficient B0 */
    __IO    uint32_t    IE;                                      /* 0x100c    Right Channel IIR1 Coefficient B1 */
    __IO    uint32_t    PD;                                      /* 0x1010    Right Channel IIR1 Coefficient B2 */
    __I     uint32_t    STA;                                     /* 0x1014    Right Channel IIR1 Coefficient A1 */
    __O     uint32_t    TBUF;                                    /* 0x1018    Right Channel IIR1 Coefficient A2 */
    __IO    uint32_t    CFG2;                                    /* 0x101c    Right Channel IIR2 Coefficient B0 */
    __IO    uint32_t    DCB;                                     /* 0x1020    Right Channel IIR2 Coefficient B1 */
    uint32_t    RESERVED4[1015];
    __IO    uint32_t    BIST_RM;                                 /* 0x2000    Right Channel IIR2 Coefficient B2 */
    __IO    uint32_t    BIST_EN;                                 /* 0x2004    Right Channel IIR2 Coefficient A1 */
    __I     uint32_t    BIST_DONE;                               /* 0x2008    Right Channel IIR2 Coefficient A2 */
    __I     uint32_t    BIST_FAIL;                               /* 0x200c    Right Channel IIR3 Coefficient B0 */
    uint32_t    RESERVED5[6140];
    __IO    uint32_t    DA_CTL;                                  /* 0x8000    Right Channel IIR3 Coefficient B1 */
    __IO    uint32_t    CP_CTL;                                  /* 0x8004    Right Channel IIR3 Coefficient B2 */
    __IO    uint32_t    HP_CTL0;                                 /* 0x8008    Right Channel IIR3 Coefficient A1 */
    __IO    uint32_t    LO_CTL0;                                 /* 0x800c    Right Channel IIR3 Coefficient A2 */
    __IO    uint32_t    LO_CTL1;                                 /* 0x8010    Right Channel IIR4 Coefficient B0 */
    __IO    uint32_t    LO_CTL2;                                 /* 0x8014    Right Channel IIR4 Coefficient B1 */
    __IO    uint32_t    HP_CTL1;                                 /* 0x8018    Right Channel IIR4 Coefficient B2 */
} DEV_DAC_RegDef;
/****DEV_DAC end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
