#ifndef __DEV_TIMER_H__
#define __DEV_TIMER_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************TIMER_IE***********************************/
#define DEV_TIMER_IE_DMA_EN3_DISABLE                            (0x0UL<<19)
#define DEV_TIMER_IE_DMA_EN3_ENABLE                             (0x1UL<<19)
#define DEV_TIMER_IE_DMA_EN3_MASK                               (0x1UL<<19)
#define DEV_TIMER_IE_DMA_EN2_DISABLE                            (0x0UL<<18)
#define DEV_TIMER_IE_DMA_EN2_ENABLE                             (0x1UL<<18)
#define DEV_TIMER_IE_DMA_EN2_MASK                               (0x1UL<<18)
#define DEV_TIMER_IE_DMA_EN1_DISABLE                            (0x0UL<<17)
#define DEV_TIMER_IE_DMA_EN1_ENABLE                             (0x1UL<<17)
#define DEV_TIMER_IE_DMA_EN1_MASK                               (0x1UL<<17)
#define DEV_TIMER_IE_DMA_EN0_DISABLE                            (0x0UL<<16)
#define DEV_TIMER_IE_DMA_EN0_ENABLE                             (0x1UL<<16)
#define DEV_TIMER_IE_DMA_EN0_MASK                               (0x1UL<<16)
#define DEV_TIMER_IE_CAPTURE3_DISABLE                           (0x0UL<<11)
#define DEV_TIMER_IE_CAPTURE3_ENABLE                            (0x1UL<<11)
#define DEV_TIMER_IE_CAPTURE3_MASK                              (0x1UL<<11)
#define DEV_TIMER_IE_CAPTURE2_DISABLE                           (0x0UL<<10)
#define DEV_TIMER_IE_CAPTURE2_ENABLE                            (0x1UL<<10)
#define DEV_TIMER_IE_CAPTURE2_MASK                              (0x1UL<<10)
#define DEV_TIMER_IE_CAPTURE1_DISABLE                           (0x0UL<<9)
#define DEV_TIMER_IE_CAPTURE1_ENABLE                            (0x1UL<<9)
#define DEV_TIMER_IE_CAPTURE1_MASK                              (0x1UL<<9)
#define DEV_TIMER_IE_CAPTURE0_DISABLE                           (0x0UL<<8)
#define DEV_TIMER_IE_CAPTURE0_ENABLE                            (0x1UL<<8)
#define DEV_TIMER_IE_CAPTURE0_MASK                              (0x1UL<<8)
#define DEV_TIMER_IE_TIMER3_DISABLE                             (0x0UL<<3)
#define DEV_TIMER_IE_TIMER3_ENABLE                              (0x1UL<<3)
#define DEV_TIMER_IE_TIMER3_MASK                                (0x1UL<<3)
#define DEV_TIMER_IE_TIMER2_DISABLE                             (0x0UL<<2)
#define DEV_TIMER_IE_TIMER2_ENABLE                              (0x1UL<<2)
#define DEV_TIMER_IE_TIMER2_MASK                                (0x1UL<<2)
#define DEV_TIMER_IE_TIMER1_DISABLE                             (0x0UL<<1)
#define DEV_TIMER_IE_TIMER1_ENABLE                              (0x1UL<<1)
#define DEV_TIMER_IE_TIMER1_MASK                                (0x1UL<<1)
#define DEV_TIMER_IE_TIMER0_DISABLE                             (0x0UL<<0)
#define DEV_TIMER_IE_TIMER0_ENABLE                              (0x1UL<<0)
#define DEV_TIMER_IE_TIMER0_MASK                                (0x1UL<<0)
/****TIMER_IE end****/


/***********************************TIMER_PD***********************************/
#define DEV_TIMER_PD_CAPTURE3                                   (0x1UL<<11)
#define DEV_TIMER_PD_CAPTURE2                                   (0x1UL<<10)
#define DEV_TIMER_PD_CAPTURE1                                   (0x1UL<<9)
#define DEV_TIMER_PD_CAPTURE0                                   (0x1UL<<8)
#define DEV_TIMER_PD_TIMER3                                     (0x1UL<<3)
#define DEV_TIMER_PD_TIMER2                                     (0x1UL<<2)
#define DEV_TIMER_PD_TIMER1                                     (0x1UL<<1)
#define DEV_TIMER_PD_TIMER0                                     (0x1UL<<0)
/****TIMER_PD end****/


/***********************************TIMERn_CTL***********************************/
#define DEV_TIMER_CTL_CAP_POL_RISE_FALL                         (0x0UL<<25)
#define DEV_TIMER_CTL_CAP_POL_FALL_RISE                         (0x1UL<<25)
#define DEV_TIMER_CTL_CAP_POL_MASK                              (0x1UL<<25)
#define DEV_TIMER_CTL_PREDIVL_MASK                              (0x1fUL<<20)
#define DEV_TIMER_CTL_CAP_FMT_DISABLE                           (0x0UL<<19)
#define DEV_TIMER_CTL_CAP_FMT_ENABLE                            (0x1UL<<19)
#define DEV_TIMER_CTL_CAP_FMT_MASK                              (0x1UL<<19)
#define DEV_TIMER_CTL_DEBOUNCE_0US                              (0x0UL<<16)
#define DEV_TIMER_CTL_DEBOUNCE_1US                              (0x1UL<<16)
#define DEV_TIMER_CTL_DEBOUNCE_2US                              (0x2UL<<16)
#define DEV_TIMER_CTL_DEBOUNCE_4US                              (0x3UL<<16)
#define DEV_TIMER_CTL_DEBOUNCE_8US                              (0x4UL<<16)
#define DEV_TIMER_CTL_DEBOUNCE_16US                             (0x5UL<<16)
#define DEV_TIMER_CTL_DEBOUNCE_32US                             (0x6UL<<16)
#define DEV_TIMER_CTL_DEBOUNCE_64US                             (0x7UL<<16)
#define DEV_TIMER_CTL_DEBOUNCE_MASK                             (0x7UL<<16)
#define DEV_TIMER_CTL_GPIO_SRC_MASK                             (0x1fUL<<8)
#define DEV_TIMER_CTL_EDGE_FREERUN                              (0x0UL<<6)
#define DEV_TIMER_CTL_EDGE_HIGHLEVEL                            (0x1UL<<6)
#define DEV_TIMER_CTL_EDGE_LOWLEVEL                             (0x2UL<<6)
#define DEV_TIMER_CTL_EDGE_MASK                                 (0x3UL<<6)
#define DEV_TIMER_CTL_MODE_TIMER                                (0x0UL<<4)
#define DEV_TIMER_CTL_MODE_COUNTER                              (0x1UL<<4)
#define DEV_TIMER_CTL_MODE_CAPTURE                              (0x2UL<<4)
#define DEV_TIMER_CTL_MODE_MASK                                 (0x3UL<<4)
#define DEV_TIMER_CTL_RESTART                                   (0x1UL<<3)
#define DEV_TIMER_CTL_DIRECTION_INCREASE                        (0x0UL<<2)
#define DEV_TIMER_CTL_DIRECTION_DECREASE                        (0x1UL<<2)
#define DEV_TIMER_CTL_DIRECTION_MASK                            (0x1UL<<2)
#define DEV_TIMER_CTL_RELOAD_EN_SINGLEMODE                      (0x0UL<<1)
#define DEV_TIMER_CTL_RELOAD_EN_RELOADMODE                      (0x1UL<<1)
#define DEV_TIMER_CTL_RELOAD_EN_MASK                            (0x1UL<<1)
#define DEV_TIMER_CTL_RUN_DISABLE                               (0x0UL<<0)
#define DEV_TIMER_CTL_RUN_ENABLE                                (0x1UL<<0)
#define DEV_TIMER_CTL_RUN_MASK                                  (0x1UL<<0)
/****TIMERn_CTL end****/


/***********************************TIMERn_LEN***********************************/
#define DEV_TIMER_LEN_LENGTH_MASK                               (0xffffffffUL<<0)
/****TIMERn_LEN end****/


/***********************************TIMERn_VAL***********************************/
#define DEV_TIMER_VAL_VALUE_MASK                                (0xffffffffUL<<0)
/****TIMERn_VAL end****/


/***********************************TIMERn_CAP***********************************/
#define DEV_TIMER_CAP_POL_LOW_FALL                              (0x0UL<<31)
#define DEV_TIMER_CAP_POL_HIGH_RISE                             (0x1UL<<31)
#define DEV_TIMER_CAP_POL_MASK                                  (0x1UL<<31)
#define DEV_TIMER_CAP_VALUE_MASK                                (0x7fffffffUL<<0)
/****TIMERn_CAP end****/


/***********************************TIMER register***********************************/
typedef struct
{

    __IO    uint32_t    CTL;                                     /* 0x20    Timer0 Control */
    __IO    uint32_t    LEN;                                     /* 0x24    Timer0 Length */
    __I     uint32_t    VAL;                                     /* 0x28    Timer0 Current Value */
    __I     uint32_t    CAP;                                     /* 0x2c    Timer0 Capture Value */
    uint32_t    RESERVED0[4];
} TIMER_RegDef;
/****TIMER end****/

/***********************************DEV_TIMER register***********************************/
typedef struct
{

    uint32_t    RESERVED0;
    __IO    uint32_t    IE;                                      /* 0x4    Timer Interrupt Enable */
    __IO    uint32_t    PD;                                      /* 0x8    Timer Interrupt Pending */
    uint32_t    RESERVED1[5];
    TIMER_RegDef    TIMER[4];                                /* 0x20    Timer0 Control */
} DEV_TIMER_RegDef;
/****DEV_TIMER end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
