#ifndef __DEV_CMU_H__
#define __DEV_CMU_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************CMU_CLKEN0***********************************/
#define DEV_CMU_CLKEN0_MPU                                      (0x1UL<<30)
#define DEV_CMU_CLKEN0_UART3                                    (0x1UL<<29)
#define DEV_CMU_CLKEN0_CAMERA                                   (0x1UL<<28)
#define DEV_CMU_CLKEN0_AON                                      (0x1UL<<27)
#define DEV_CMU_CLKEN0_UDSP                                     (0x1UL<<26)
#define DEV_CMU_CLKEN0_NPU                                      (0x1UL<<25)
#define DEV_CMU_CLKEN0_SRC                                      (0x1UL<<24)
#define DEV_CMU_CLKEN0_DAC                                      (0x1UL<<23)
#define DEV_CMU_CLKEN0_ADC                                      (0x1UL<<22)
#define DEV_CMU_CLKEN0_USB                                      (0x1UL<<20)
#define DEV_CMU_CLKEN0_SDC                                      (0x1UL<<19)
#define DEV_CMU_CLKEN0_PWM                                      (0x1UL<<18)
#define DEV_CMU_CLKEN0_IRTX                                     (0x1UL<<17)
#define DEV_CMU_CLKEN0_IRRX                                     (0x1UL<<16)
#define DEV_CMU_CLKEN0_ASI1                                     (0x1UL<<15)
#define DEV_CMU_CLKEN0_ASI0                                     (0x1UL<<14)
#define DEV_CMU_CLKEN0_I2C1                                     (0x1UL<<13)
#define DEV_CMU_CLKEN0_I2C0                                     (0x1UL<<12)
#define DEV_CMU_CLKEN0_UART2                                    (0x1UL<<11)
#define DEV_CMU_CLKEN0_UART1                                    (0x1UL<<10)
#define DEV_CMU_CLKEN0_UART0                                    (0x1UL<<9)
#define DEV_CMU_CLKEN0_SPI1                                     (0x1UL<<8)
#define DEV_CMU_CLKEN0_SPI0                                     (0x1UL<<7)
#define DEV_CMU_CLKEN0_TICK                                     (0x1UL<<6)
#define DEV_CMU_CLKEN0_TIMER                                    (0x1UL<<5)
#define DEV_CMU_CLKEN0_EINT                                     (0x1UL<<4)
#define DEV_CMU_CLKEN0_ASU                                      (0x1UL<<3)
#define DEV_CMU_CLKEN0_EFUSE                                    (0x1UL<<2)
#define DEV_CMU_CLKEN0_GPIO                                     (0x1UL<<1)
#define DEV_CMU_CLKEN0_DMA                                      (0x1UL<<0)
/****CMU_CLKEN0 end****/


/***********************************CMU_CLKEN1***********************************/
#define DEV_CMU_CLKEN1_PSRAM                                    (0x1UL<<15)
#define DEV_CMU_CLKEN1_MEM                                      (0x1UL<<14)
#define DEV_CMU_CLKEN1_HST                                      (0x1UL<<13)
#define DEV_CMU_CLKEN1_DEV                                      (0x1UL<<12)
#define DEV_CMU_CLKEN1_RAM7                                     (0x1UL<<11)
#define DEV_CMU_CLKEN1_RAM6                                     (0x1UL<<10)
#define DEV_CMU_CLKEN1_RAM5                                     (0x1UL<<9)
#define DEV_CMU_CLKEN1_RAM4                                     (0x1UL<<8)
#define DEV_CMU_CLKEN1_RAM3                                     (0x1UL<<7)
#define DEV_CMU_CLKEN1_RAM2                                     (0x1UL<<6)
#define DEV_CMU_CLKEN1_RAM1                                     (0x1UL<<5)
#define DEV_CMU_CLKEN1_RAM0                                     (0x1UL<<4)
#define DEV_CMU_CLKEN1_CACHE                                    (0x1UL<<3)
#define DEV_CMU_CLKEN1_NORC                                     (0x1UL<<2)
#define DEV_CMU_CLKEN1_SYS                                      (0x1UL<<1)
#define DEV_CMU_CLKEN1_CPU                                      (0x1UL<<0)
/****CMU_CLKEN1 end****/


/***********************************CMU_SYSCLK***********************************/
#define DEV_CMU_SYSCLK_SYS_DIV_1                                (0x0UL<<8)
#define DEV_CMU_SYSCLK_SYS_DIV_2                                (0x1UL<<8)
#define DEV_CMU_SYSCLK_SYS_DIV_4                                (0x2UL<<8)
#define DEV_CMU_SYSCLK_SYS_DIV_8                                (0x3UL<<8)
#define DEV_CMU_SYSCLK_SYS_DIV_12                               (0x4UL<<8)
#define DEV_CMU_SYSCLK_SYS_DIV_16                               (0x5UL<<8)
#define DEV_CMU_SYSCLK_SYS_DIV_24                               (0x6UL<<8)
#define DEV_CMU_SYSCLK_SYS_DIV_32                               (0x7UL<<8)
#define DEV_CMU_SYSCLK_SYS_DIV_MASK                             (0x7UL<<8)
#define DEV_CMU_SYSCLK_CORE_DIV_1                               (0x0UL<<4)
#define DEV_CMU_SYSCLK_CORE_DIV_2                               (0x1UL<<4)
#define DEV_CMU_SYSCLK_CORE_DIV_4                               (0x2UL<<4)
#define DEV_CMU_SYSCLK_CORE_DIV_8                               (0x3UL<<4)
#define DEV_CMU_SYSCLK_CORE_DIV_12                              (0x4UL<<4)
#define DEV_CMU_SYSCLK_CORE_DIV_16                              (0x5UL<<4)
#define DEV_CMU_SYSCLK_CORE_DIV_24                              (0x6UL<<4)
#define DEV_CMU_SYSCLK_CORE_DIV_32                              (0x7UL<<4)
#define DEV_CMU_SYSCLK_CORE_DIV_MASK                            (0x7UL<<4)
#define DEV_CMU_SYSCLK_CORE_SEL_OSC_ADC                         (0x0UL<<0)
#define DEV_CMU_SYSCLK_CORE_SEL_OSC_DEV                         (0x1UL<<0)
#define DEV_CMU_SYSCLK_CORE_SEL_OSC_XTAL                        (0x2UL<<0)
#define DEV_CMU_SYSCLK_CORE_SEL_OSC_USB                         (0x3UL<<0)
#define DEV_CMU_SYSCLK_CORE_SEL_PLL_CORE                        (0x4UL<<0)
#define DEV_CMU_SYSCLK_CORE_SEL_PLL_USB                         (0x5UL<<0)
#define DEV_CMU_SYSCLK_CORE_SEL_EXT_CLK                         (0x6UL<<0)
#define DEV_CMU_SYSCLK_CORE_SEL_MASK                            (0x7UL<<0)
/****CMU_SYSCLK end****/


/***********************************CMU_SPInCLK***********************************/
#define DEV_CMU_SPInCLK_DIV_1                                   (0x0UL<<4)
#define DEV_CMU_SPInCLK_DIV_2                                   (0x1UL<<4)
#define DEV_CMU_SPInCLK_DIV_4                                   (0x2UL<<4)
#define DEV_CMU_SPInCLK_DIV_8                                   (0x3UL<<4)
#define DEV_CMU_SPInCLK_DIV_12                                  (0x4UL<<4)
#define DEV_CMU_SPInCLK_DIV_16                                  (0x5UL<<4)
#define DEV_CMU_SPInCLK_DIV_24                                  (0x6UL<<4)
#define DEV_CMU_SPInCLK_DIV_32                                  (0x7UL<<4)
#define DEV_CMU_SPInCLK_DIV_MASK                                (0x7UL<<4)
#define DEV_CMU_SPInCLK_SEL_OSC_DEV                             (0x0UL<<0)
#define DEV_CMU_SPInCLK_SEL_OSC_XTAL                            (0x1UL<<0)
#define DEV_CMU_SPInCLK_SEL_OSC_USB                             (0x2UL<<0)
#define DEV_CMU_SPInCLK_SEL_PLL_CORE                            (0x3UL<<0)
#define DEV_CMU_SPInCLK_SEL_EXT_CLK                             (0x4UL<<0)
#define DEV_CMU_SPInCLK_SEL_MASK                                (0x7UL<<0)
/****CMU_SPInCLK end****/


/***********************************CMU_I2CnCLK***********************************/
#define DEV_CMU_I2CnCLK_SEL_OSC_DEV                             (0x0UL<<0)
#define DEV_CMU_I2CnCLK_SEL_OSC_XTAL                            (0x1UL<<0)
#define DEV_CMU_I2CnCLK_SEL_OSC_USB                             (0x2UL<<0)
#define DEV_CMU_I2CnCLK_SEL_EXT_CLK                             (0x3UL<<0)
#define DEV_CMU_I2CnCLK_SEL_MASK                                (0x3UL<<0)
/****CMU_I2CnCLK end****/


/***********************************CMU_UARTnCLK***********************************/
#define DEV_CMU_UARTnCLK_SEL_OSC_DEV                            (0x0UL<<0)
#define DEV_CMU_UARTnCLK_SEL_OSC_XTAL                           (0x1UL<<0)
#define DEV_CMU_UARTnCLK_SEL_OSC_USB                            (0x2UL<<0)
#define DEV_CMU_UARTnCLK_SEL_EXT_CLK                            (0x3UL<<0)
#define DEV_CMU_UARTnCLK_SEL_MASK                               (0x3UL<<0)
/****CMU_UARTnCLK end****/


/***********************************CMU_NOR0CLK***********************************/
#define DEV_CMU_NOR0CLK_DIV_1                                   (0x0UL<<4)
#define DEV_CMU_NOR0CLK_DIV_2                                   (0x1UL<<4)
#define DEV_CMU_NOR0CLK_DIV_4                                   (0x2UL<<4)
#define DEV_CMU_NOR0CLK_DIV_8                                   (0x3UL<<4)
#define DEV_CMU_NOR0CLK_DIV_12                                  (0x4UL<<4)
#define DEV_CMU_NOR0CLK_DIV_16                                  (0x5UL<<4)
#define DEV_CMU_NOR0CLK_DIV_24                                  (0x6UL<<4)
#define DEV_CMU_NOR0CLK_DIV_32                                  (0x7UL<<4)
#define DEV_CMU_NOR0CLK_DIV_MASK                                (0x7UL<<4)
#define DEV_CMU_NOR0CLK_SEL_SYS_CLK                             (0x0UL<<0)
#define DEV_CMU_NOR0CLK_SEL_OSC_DEV                             (0x1UL<<0)
#define DEV_CMU_NOR0CLK_SEL_OSC_XTAL                            (0x2UL<<0)
#define DEV_CMU_NOR0CLK_SEL_OSC_USB                             (0x3UL<<0)
#define DEV_CMU_NOR0CLK_SEL_PLL_CORE                            (0x4UL<<0)
#define DEV_CMU_NOR0CLK_SEL_PLL_USB                             (0x5UL<<0)
#define DEV_CMU_NOR0CLK_SEL_EXT_CLK                             (0x6UL<<0)
#define DEV_CMU_NOR0CLK_SEL_MASK                                (0x7UL<<0)
/****CMU_NOR0CLK end****/


/***********************************CMU_PWMnCLK***********************************/
#define DEV_CMU_PWMnCLK_DIV_MASK                                (0x1fffUL<<4)
#define DEV_CMU_PWMnCLK_SEL_OSC_ADC                             (0x0UL<<1)
#define DEV_CMU_PWMnCLK_SEL_OSC_DEV                             (0x1UL<<1)
#define DEV_CMU_PWMnCLK_SEL_OSC_XTAL                            (0x2UL<<1)
#define DEV_CMU_PWMnCLK_SEL_OSC_USB                             (0x3UL<<1)
#define DEV_CMU_PWMnCLK_SEL_PLL_CORE                            (0x4UL<<1)
#define DEV_CMU_PWMnCLK_SEL_PLL_AUDIO                           (0x5UL<<1)
#define DEV_CMU_PWMnCLK_SEL_EXT_CLK                             (0x6UL<<1)
#define DEV_CMU_PWMnCLK_SEL_MASK                                (0x7UL<<1)
#define DEV_CMU_PWMnCLK_EN_DISABLE                              (0x0UL<<0)
#define DEV_CMU_PWMnCLK_EN_ENABLE                               (0x1UL<<0)
#define DEV_CMU_PWMnCLK_EN_MASK                                 (0x1UL<<0)
/****CMU_PWMnCLK end****/


/***********************************CMU_TIMERnCLK***********************************/
#define DEV_CMU_TIMERnCLK_SEL_OSC_ADC                           (0x0UL<<1)
#define DEV_CMU_TIMERnCLK_SEL_OSC_DEV                           (0x1UL<<1)
#define DEV_CMU_TIMERnCLK_SEL_OSC_XTAL                          (0x2UL<<1)
#define DEV_CMU_TIMERnCLK_SEL_OSC_USB                           (0x3UL<<1)
#define DEV_CMU_TIMERnCLK_SEL_PLL_CORE                          (0x4UL<<1)
#define DEV_CMU_TIMERnCLK_SEL_PLL_AUDIO                         (0x5UL<<1)
#define DEV_CMU_TIMERnCLK_SEL_USB_SOF                           (0x6UL<<1)
#define DEV_CMU_TIMERnCLK_SEL_EXT_CLK                           (0x7UL<<1)
#define DEV_CMU_TIMERnCLK_SEL_MASK                              (0x7UL<<1)
#define DEV_CMU_TIMERnCLK_EN_DISABLE                            (0x0UL<<0)
#define DEV_CMU_TIMERnCLK_EN_ENABLE                             (0x1UL<<0)
#define DEV_CMU_TIMERnCLK_EN_MASK                               (0x1UL<<0)
/****CMU_TIMERnCLK end****/


/***********************************CMU_ADCCLK***********************************/
#define DEV_CMU_ADCCLK_DIV_MASK                                 (0xffUL<<4)
#define DEV_CMU_ADCCLK_SEL_OSC_DEV                              (0x0UL<<1)
#define DEV_CMU_ADCCLK_SEL_OSC_XTAL                             (0x1UL<<1)
#define DEV_CMU_ADCCLK_SEL_OSC_USB                              (0x2UL<<1)
#define DEV_CMU_ADCCLK_SEL_PLL_AUDIO                            (0x3UL<<1)
#define DEV_CMU_ADCCLK_SEL_EXT_CLK                              (0x4UL<<1)
#define DEV_CMU_ADCCLK_SEL_MASK                                 (0x7UL<<1)
#define DEV_CMU_ADCCLK_EN_DISABLE                               (0x0UL<<0)
#define DEV_CMU_ADCCLK_EN_ENABLE                                (0x1UL<<0)
#define DEV_CMU_ADCCLK_EN_MASK                                  (0x1UL<<0)
/****CMU_ADCCLK end****/


/***********************************CMU_DACCLK***********************************/
#define DEV_CMU_DACCLK_ANA_DIV_MASK                             (0x3UL<<8)
#define DEV_CMU_DACCLK_DIG_DIV_MASK                             (0xfUL<<4)
#define DEV_CMU_DACCLK_SEL_OSC_DEV                              (0x0UL<<1)
#define DEV_CMU_DACCLK_SEL_OSC_XTAL                             (0x1UL<<1)
#define DEV_CMU_DACCLK_SEL_OSC_USB                              (0x2UL<<1)
#define DEV_CMU_DACCLK_SEL_PLL_AUDIO                            (0x3UL<<1)
#define DEV_CMU_DACCLK_SEL_EXT_CLK                              (0x4UL<<1)
#define DEV_CMU_DACCLK_SEL_ADC_CLK                              (0x5UL<<1)
#define DEV_CMU_DACCLK_SEL_MASK                                 (0x7UL<<1)
#define DEV_CMU_DACCLK_EN_DISABLE                               (0x0UL<<0)
#define DEV_CMU_DACCLK_EN_ENABLE                                (0x1UL<<0)
#define DEV_CMU_DACCLK_EN_MASK                                  (0x1UL<<0)
/****CMU_DACCLK end****/


/***********************************CMU_ASInCLK***********************************/
#define DEV_CMU_ASInCLK_DIV_MASK                                (0xffUL<<4)
#define DEV_CMU_ASInCLK_SEL_OSC_DEV                             (0x0UL<<0)
#define DEV_CMU_ASInCLK_SEL_OSC_XTAL                            (0x1UL<<0)
#define DEV_CMU_ASInCLK_SEL_OSC_USB                             (0x2UL<<0)
#define DEV_CMU_ASInCLK_SEL_PLL_AUDIO                           (0x3UL<<0)
#define DEV_CMU_ASInCLK_SEL_EXT_CLK                             (0x4UL<<0)
#define DEV_CMU_ASInCLK_SEL_MASK                                (0x7UL<<0)
/****CMU_ASInCLK end****/


/***********************************CMU_IRRXCLK***********************************/
#define DEV_CMU_IRRXCLK_DIV_MASK                                (0xffUL<<4)
#define DEV_CMU_IRRXCLK_SEL_OSC_DEV                             (0x0UL<<0)
#define DEV_CMU_IRRXCLK_SEL_OSC_XTAL                            (0x1UL<<0)
#define DEV_CMU_IRRXCLK_SEL_OSC_USB                             (0x2UL<<0)
#define DEV_CMU_IRRXCLK_SEL_EXT_CLK                             (0x3UL<<0)
#define DEV_CMU_IRRXCLK_SEL_MASK                                (0x3UL<<0)
/****CMU_IRRXCLK end****/


/***********************************CMU_IRTXCLK***********************************/
#define DEV_CMU_IRTXCLK_DIV_MASK                                (0xfUL<<4)
#define DEV_CMU_IRTXCLK_SEL_OSC_DEV                             (0x0UL<<0)
#define DEV_CMU_IRTXCLK_SEL_OSC_XTAL                            (0x1UL<<0)
#define DEV_CMU_IRTXCLK_SEL_OSC_USB                             (0x2UL<<0)
#define DEV_CMU_IRTXCLK_SEL_EXT_CLK                             (0x3UL<<0)
#define DEV_CMU_IRTXCLK_SEL_MASK                                (0x3UL<<0)
/****CMU_IRTXCLK end****/


/***********************************CMU_TICKCLK***********************************/
#define DEV_CMU_TICKCLK_DIV_4                                   (0x0UL<<4)
#define DEV_CMU_TICKCLK_DIV_16                                  (0x1UL<<4)
#define DEV_CMU_TICKCLK_DIV_24                                  (0x2UL<<4)
#define DEV_CMU_TICKCLK_DIV_30                                  (0x3UL<<4)
#define DEV_CMU_TICKCLK_DIV_MASK                                (0x3UL<<4)
#define DEV_CMU_TICKCLK_SEL_SYS_CLK                             (0x0UL<<0)
#define DEV_CMU_TICKCLK_SEL_OSC_ADC                             (0x1UL<<0)
#define DEV_CMU_TICKCLK_SEL_OSC_DEV                             (0x2UL<<0)
#define DEV_CMU_TICKCLK_SEL_OSC_XTAL                            (0x3UL<<0)
#define DEV_CMU_TICKCLK_SEL_OSC_USB                             (0x4UL<<0)
#define DEV_CMU_TICKCLK_SEL_EXT_CLK                             (0x5UL<<0)
#define DEV_CMU_TICKCLK_SEL_MASK                                (0x7UL<<0)
/****CMU_TICKCLK end****/


/***********************************CMU_SDCCLK***********************************/
#define DEV_CMU_SDCCLK_DIV_MASK                                 (0xffUL<<4)
#define DEV_CMU_SDCCLK_SEL_SYS_CLK                              (0x0UL<<0)
#define DEV_CMU_SDCCLK_SEL_OSC_DEV                              (0x1UL<<0)
#define DEV_CMU_SDCCLK_SEL_OSC_XTAL                             (0x2UL<<0)
#define DEV_CMU_SDCCLK_SEL_OSC_USB                              (0x3UL<<0)
#define DEV_CMU_SDCCLK_SEL_PLL_CORE                             (0x4UL<<0)
#define DEV_CMU_SDCCLK_SEL_EXT_CLK                              (0x5UL<<0)
#define DEV_CMU_SDCCLK_SEL_MASK                                 (0x7UL<<0)
/****CMU_SDCCLK end****/


/***********************************CMU_USBCLK***********************************/
#define DEV_CMU_USBCLK_SEL_OSC_DEV_2                            (0x0UL<<2)
#define DEV_CMU_USBCLK_SEL_OSC_XTAL_2                           (0x1UL<<2)
#define DEV_CMU_USBCLK_SEL_EXT_CLK_2                            (0x2UL<<2)
#define DEV_CMU_USBCLK_SEL_MASK                                 (0x3UL<<2)
#define DEV_CMU_USBCLK_EN_DISABLE                               (0x0UL<<0)
#define DEV_CMU_USBCLK_EN_ENABLE                                (0x1UL<<0)
#define DEV_CMU_USBCLK_EN_MASK                                  (0x1UL<<0)
/****CMU_USBCLK end****/


/***********************************CMU_CP2CLK***********************************/
#define DEV_CMU_CP2CLK_DIV_MASK                                 (0xfUL<<4)
#define DEV_CMU_CP2CLK_SEL_OSC_DEV                              (0x0UL<<2)
#define DEV_CMU_CP2CLK_SEL_OSC_XTAL                             (0x1UL<<2)
#define DEV_CMU_CP2CLK_SEL_OSC_USB                              (0x2UL<<2)
#define DEV_CMU_CP2CLK_SEL_EXT_CLK                              (0x3UL<<2)
#define DEV_CMU_CP2CLK_SEL_MASK                                 (0x3UL<<2)
#define DEV_CMU_CP2CLK_EN_DISABLE                               (0x0UL<<0)
#define DEV_CMU_CP2CLK_EN_ENABLE                                (0x1UL<<0)
#define DEV_CMU_CP2CLK_EN_MASK                                  (0x1UL<<0)
/****CMU_CP2CLK end****/


/***********************************CMU_HSCALCLK***********************************/
#define DEV_CMU_HSCALCLK_SEL_128K                               (0x0UL<<1)
#define DEV_CMU_HSCALCLK_SEL_64K                                (0x1UL<<1)
#define DEV_CMU_HSCALCLK_SEL_32K                                (0x2UL<<1)
#define DEV_CMU_HSCALCLK_SEL_16K                                (0x3UL<<1)
#define DEV_CMU_HSCALCLK_SEL_8K                                 (0x4UL<<1)
#define DEV_CMU_HSCALCLK_SEL_4K                                 (0x5UL<<1)
#define DEV_CMU_HSCALCLK_SEL_2K                                 (0x6UL<<1)
#define DEV_CMU_HSCALCLK_SEL_MASK                               (0x7UL<<1)
#define DEV_CMU_HSCALCLK_EN_DISABLE                             (0x0UL<<0)
#define DEV_CMU_HSCALCLK_EN_ENABLE                              (0x1UL<<0)
#define DEV_CMU_HSCALCLK_EN_MASK                                (0x1UL<<0)
/****CMU_HSCALCLK end****/


/***********************************CMU_DLYCLK***********************************/
#define DEV_CMU_DLYCLK_SEL_OSC_DEV                              (0x0UL<<1)
#define DEV_CMU_DLYCLK_SEL_OSC_XTAL                             (0x1UL<<1)
#define DEV_CMU_DLYCLK_SEL_OSC_USB                              (0x2UL<<1)
#define DEV_CMU_DLYCLK_SEL_MASK                                 (0x3UL<<1)
#define DEV_CMU_DLYCLK_EN_DISABLE                               (0x0UL<<0)
#define DEV_CMU_DLYCLK_EN_ENABLE                                (0x1UL<<0)
#define DEV_CMU_DLYCLK_EN_MASK                                  (0x1UL<<0)
/****CMU_DLYCLK end****/


/***********************************CMU_CAMERACLK***********************************/
#define DEV_CMU_CAMERACLK_DIV_1                                 (0x0UL<<4)
#define DEV_CMU_CAMERACLK_DIV_2                                 (0x1UL<<4)
#define DEV_CMU_CAMERACLK_DIV_4                                 (0x2UL<<4)
#define DEV_CMU_CAMERACLK_DIV_8                                 (0x3UL<<4)
#define DEV_CMU_CAMERACLK_DIV_12                                (0x4UL<<4)
#define DEV_CMU_CAMERACLK_DIV_16                                (0x5UL<<4)
#define DEV_CMU_CAMERACLK_DIV_24                                (0x6UL<<4)
#define DEV_CMU_CAMERACLK_DIV_32                                (0x7UL<<4)
#define DEV_CMU_CAMERACLK_DIV_MASK                              (0x7UL<<4)
#define DEV_CMU_CAMERACLK_SEL_OSC_DEV                           (0x0UL<<0)
#define DEV_CMU_CAMERACLK_SEL_OSC_XTAL                          (0x1UL<<0)
#define DEV_CMU_CAMERACLK_SEL_OSC_USB                           (0x2UL<<0)
#define DEV_CMU_CAMERACLK_SEL_PLL_CORE                          (0x3UL<<0)
#define DEV_CMU_CAMERACLK_SEL_EXT_CLK                           (0x5UL<<0)
#define DEV_CMU_CAMERACLK_SEL_MASK                              (0x7UL<<0)
/****CMU_CAMERACLK end****/


/***********************************CMU_UART3CLK***********************************/
#define DEV_CMU_UART3CLK_SEL_OSC_DEV                            (0x0UL<<0)
#define DEV_CMU_UART3CLK_SEL_OSC_XTAL                           (0x1UL<<0)
#define DEV_CMU_UART3CLK_SEL_OSC_USB                            (0x2UL<<0)
#define DEV_CMU_UART3CLK_SEL_EXT_CLK                            (0x3UL<<0)
#define DEV_CMU_UART3CLK_SEL_MASK                               (0x3UL<<0)
/****CMU_UART3CLK end****/


/***********************************CMU_PSRAMCLK***********************************/
#define DEV_CMU_PSRAMCLK_DIV_1                                  (0x0UL<<4)
#define DEV_CMU_PSRAMCLK_DIV_2                                  (0x1UL<<4)
#define DEV_CMU_PSRAMCLK_DIV_4                                  (0x2UL<<4)
#define DEV_CMU_PSRAMCLK_DIV_8                                  (0x3UL<<4)
#define DEV_CMU_PSRAMCLK_DIV_12                                 (0x4UL<<4)
#define DEV_CMU_PSRAMCLK_DIV_16                                 (0x5UL<<4)
#define DEV_CMU_PSRAMCLK_DIV_24                                 (0x6UL<<4)
#define DEV_CMU_PSRAMCLK_DIV_32                                 (0x7UL<<4)
#define DEV_CMU_PSRAMCLK_DIV_MASK                               (0x7UL<<4)
#define DEV_CMU_PSRAMCLK_SEL_SYS_CLK                            (0x0UL<<0)
#define DEV_CMU_PSRAMCLK_SEL_OSC_DEV                            (0x1UL<<0)
#define DEV_CMU_PSRAMCLK_SEL_OSC_XTAL                           (0x2UL<<0)
#define DEV_CMU_PSRAMCLK_SEL_OSC_USB                            (0x3UL<<0)
#define DEV_CMU_PSRAMCLK_SEL_PLL_CORE                           (0x4UL<<0)
#define DEV_CMU_PSRAMCLK_SEL_PLL_USB                            (0x5UL<<0)
#define DEV_CMU_PSRAMCLK_SEL_EXT_CLK                            (0x6UL<<0)
#define DEV_CMU_PSRAMCLK_SEL_MASK                               (0x7UL<<0)
/****CMU_PSRAMCLK end****/


/***********************************CMU_CLKDET***********************************/
#define DEV_CMU_CLKDET_EXT_CLK2_DET_DISABLE                     (0x0UL<<7)
#define DEV_CMU_CLKDET_EXT_CLK2_DET_ENABLE                      (0x1UL<<7)
#define DEV_CMU_CLKDET_EXT_CLK2_DET_MASK                        (0x1UL<<7)
#define DEV_CMU_CLKDET_EXT_CLK_DET_DISABLE                      (0x0UL<<6)
#define DEV_CMU_CLKDET_EXT_CLK_DET_ENABLE                       (0x1UL<<6)
#define DEV_CMU_CLKDET_EXT_CLK_DET_MASK                         (0x1UL<<6)
#define DEV_CMU_CLKDET_PLL_USB_DET_DISABLE                      (0x0UL<<5)
#define DEV_CMU_CLKDET_PLL_USB_DET_ENABLE                       (0x1UL<<5)
#define DEV_CMU_CLKDET_PLL_USB_DET_MASK                         (0x1UL<<5)
#define DEV_CMU_CLKDET_PLL_AUDIO_DET_DISABLE                    (0x0UL<<4)
#define DEV_CMU_CLKDET_PLL_AUDIO_DET_ENABLE                     (0x1UL<<4)
#define DEV_CMU_CLKDET_PLL_AUDIO_DET_MASK                       (0x1UL<<4)
#define DEV_CMU_CLKDET_PLL_CORE_DET_DISABLE                     (0x0UL<<3)
#define DEV_CMU_CLKDET_PLL_CORE_DET_ENABLE                      (0x1UL<<3)
#define DEV_CMU_CLKDET_PLL_CORE_DET_MASK                        (0x1UL<<3)
#define DEV_CMU_CLKDET_OSC_USB_DET_DISABLE                      (0x0UL<<2)
#define DEV_CMU_CLKDET_OSC_USB_DET_ENABLE                       (0x1UL<<2)
#define DEV_CMU_CLKDET_OSC_USB_DET_MASK                         (0x1UL<<2)
#define DEV_CMU_CLKDET_OSC_XTAL_DET_DISABLE                     (0x0UL<<1)
#define DEV_CMU_CLKDET_OSC_XTAL_DET_ENABLE                      (0x1UL<<1)
#define DEV_CMU_CLKDET_OSC_XTAL_DET_MASK                        (0x1UL<<1)
#define DEV_CMU_CLKDET_OSC_DEV_DET_DISABLE                      (0x0UL<<0)
#define DEV_CMU_CLKDET_OSC_DEV_DET_ENABLE                       (0x1UL<<0)
#define DEV_CMU_CLKDET_OSC_DEV_DET_MASK                         (0x1UL<<0)
/****CMU_CLKDET end****/


/***********************************CMU_CLKRDY***********************************/
#define DEV_CMU_CLKRDY_EXT_CLK2_RDY                             (0x1UL<<7)
#define DEV_CMU_CLKRDY_EXT_CLK_RDY                              (0x1UL<<6)
#define DEV_CMU_CLKRDY_PLL_USB_RDY                              (0x1UL<<5)
#define DEV_CMU_CLKRDY_PLL_AUDIO_RDY                            (0x1UL<<4)
#define DEV_CMU_CLKRDY_PLL_CORE_RDY                             (0x1UL<<3)
#define DEV_CMU_CLKRDY_OSC_USB_RDY                              (0x1UL<<2)
#define DEV_CMU_CLKRDY_OSC_XTAL_RDY                             (0x1UL<<1)
#define DEV_CMU_CLKRDY_OSC_DEV_RDY                              (0x1UL<<0)
/****CMU_CLKRDY end****/


/***********************************CMU_DBGCTL***********************************/
#define DEV_CMU_DBGCTL_DIV_1                                    (0x0UL<<8)
#define DEV_CMU_DBGCTL_DIV_2                                    (0x1UL<<8)
#define DEV_CMU_DBGCTL_DIV_4                                    (0x2UL<<8)
#define DEV_CMU_DBGCTL_DIV_8                                    (0x3UL<<8)
#define DEV_CMU_DBGCTL_DIV_16                                   (0x4UL<<8)
#define DEV_CMU_DBGCTL_DIV_32                                   (0x5UL<<8)
#define DEV_CMU_DBGCTL_DIV_64                                   (0x6UL<<8)
#define DEV_CMU_DBGCTL_DIV_128                                  (0x7UL<<8)
#define DEV_CMU_DBGCTL_DIV_MASK                                 (0x7UL<<8)
#define DEV_CMU_DBGCTL_SEL_0                                    (0x0UL<<0)
#define DEV_CMU_DBGCTL_SEL_OSC_ADC                              (0x1UL<<0)
#define DEV_CMU_DBGCTL_SEL_OSC_DEV                              (0x2UL<<0)
#define DEV_CMU_DBGCTL_SEL_OSC_USB                              (0x3UL<<0)
#define DEV_CMU_DBGCTL_SEL_OSC_XTAL                             (0x4UL<<0)
#define DEV_CMU_DBGCTL_SEL_PLL_CORE                             (0x5UL<<0)
#define DEV_CMU_DBGCTL_SEL_PLL_AUDIO                            (0x6UL<<0)
#define DEV_CMU_DBGCTL_SEL_PLL_USB                              (0x7UL<<0)
#define DEV_CMU_DBGCTL_SEL_USB_SOF                              (0x8UL<<0)
#define DEV_CMU_DBGCTL_SEL_EXT_CLK                              (0x9UL<<0)
#define DEV_CMU_DBGCTL_SEL_EXT_CLK2                             (0xaUL<<0)
#define DEV_CMU_DBGCTL_SEL_SYS_CLK                              (0xbUL<<0)
#define DEV_CMU_DBGCTL_SEL_CPU_CLK                              (0xcUL<<0)
#define DEV_CMU_DBGCTL_SEL_SYS_DIV_EN                           (0xdUL<<0)
#define DEV_CMU_DBGCTL_SEL_UDSP_CLK                             (0xeUL<<0)
#define DEV_CMU_DBGCTL_SEL_NPU_CLK                              (0xfUL<<0)
#define DEV_CMU_DBGCTL_SEL_DMA_CLK                              (0x10UL<<0)
#define DEV_CMU_DBGCTL_SEL_ASU_CLK                              (0x11UL<<0)
#define DEV_CMU_DBGCTL_SEL_DEV_CLK                              (0x12UL<<0)
#define DEV_CMU_DBGCTL_SEL_HST_CLK                              (0x13UL<<0)
#define DEV_CMU_DBGCTL_SEL_MEM_CLK                              (0x14UL<<0)
#define DEV_CMU_DBGCTL_SEL_EINT_CLK                             (0x15UL<<0)
#define DEV_CMU_DBGCTL_SEL_EFUSE_CLK                            (0x16UL<<0)
#define DEV_CMU_DBGCTL_SEL_DLY_CLK                              (0x17UL<<0)
#define DEV_CMU_DBGCTL_SEL_TICK_CLK                             (0x18UL<<0)
#define DEV_CMU_DBGCTL_SEL_USB_CLK                              (0x19UL<<0)
#define DEV_CMU_DBGCTL_SEL_RAM0_CLK                             (0x1aUL<<0)
#define DEV_CMU_DBGCTL_SEL_RAM1_CLK                             (0x1bUL<<0)
#define DEV_CMU_DBGCTL_SEL_RAM2_CLK                             (0x1cUL<<0)
#define DEV_CMU_DBGCTL_SEL_RAM3_CLK                             (0x1dUL<<0)
#define DEV_CMU_DBGCTL_SEL_RAM4_CLK                             (0x1eUL<<0)
#define DEV_CMU_DBGCTL_SEL_RAM5_CLK                             (0x1fUL<<0)
#define DEV_CMU_DBGCTL_SEL_RAM6_CLK                             (0x20UL<<0)
#define DEV_CMU_DBGCTL_SEL_RAM7_CLK                             (0x21UL<<0)
#define DEV_CMU_DBGCTL_SEL_NOR0_MCLK                            (0x22UL<<0)
#define DEV_CMU_DBGCTL_SEL_NOR0_CLK                             (0x23UL<<0)
#define DEV_CMU_DBGCTL_SEL_SPI0_CLK                             (0x24UL<<0)
#define DEV_CMU_DBGCTL_SEL_SPI1_CLK                             (0x25UL<<0)
#define DEV_CMU_DBGCTL_SEL_I2C0_CLK                             (0x26UL<<0)
#define DEV_CMU_DBGCTL_SEL_I2C1_CLK                             (0x27UL<<0)
#define DEV_CMU_DBGCTL_SEL_UART0_CLK                            (0x28UL<<0)
#define DEV_CMU_DBGCTL_SEL_UART1_CLK                            (0x29UL<<0)
#define DEV_CMU_DBGCTL_SEL_UART2_CLK                            (0x2aUL<<0)
#define DEV_CMU_DBGCTL_SEL_UART3_CLK                            (0x2bUL<<0)
#define DEV_CMU_DBGCTL_SEL_PWM0_CLK                             (0x2cUL<<0)
#define DEV_CMU_DBGCTL_SEL_PWM1_CLK                             (0x2dUL<<0)
#define DEV_CMU_DBGCTL_SEL_PWM2_CLK                             (0x2eUL<<0)
#define DEV_CMU_DBGCTL_SEL_PWM3_CLK                             (0x2fUL<<0)
#define DEV_CMU_DBGCTL_SEL_PWM4_CLK                             (0x30UL<<0)
#define DEV_CMU_DBGCTL_SEL_PWM5_CLK                             (0x31UL<<0)
#define DEV_CMU_DBGCTL_SEL_PWM6_CLK                             (0x32UL<<0)
#define DEV_CMU_DBGCTL_SEL_PWM7_CLK                             (0x33UL<<0)
#define DEV_CMU_DBGCTL_SEL_ASI0_CLK                             (0x34UL<<0)
#define DEV_CMU_DBGCTL_SEL_ASI1_CLK                             (0x35UL<<0)
#define DEV_CMU_DBGCTL_SEL_CACHE_MCLK                           (0x36UL<<0)
#define DEV_CMU_DBGCTL_SEL_ADC_CLK                              (0x37UL<<0)
#define DEV_CMU_DBGCTL_SEL_DAC_CLK                              (0x38UL<<0)
#define DEV_CMU_DBGCTL_SEL_TIMER0_CLK                           (0x39UL<<0)
#define DEV_CMU_DBGCTL_SEL_TIMER1_CLK                           (0x3aUL<<0)
#define DEV_CMU_DBGCTL_SEL_TIMER2_CLK                           (0x3bUL<<0)
#define DEV_CMU_DBGCTL_SEL_TIMER3_CLK                           (0x3cUL<<0)
#define DEV_CMU_DBGCTL_SEL_SDC_CLK                              (0x3dUL<<0)
#define DEV_CMU_DBGCTL_SEL_IRRX_CLK                             (0x3eUL<<0)
#define DEV_CMU_DBGCTL_SEL_IRTX_CLK                             (0x3fUL<<0)
#define DEV_CMU_DBGCTL_SEL_CP2_CLK                              (0x40UL<<0)
#define DEV_CMU_DBGCTL_SEL_HSCAL_CLK                            (0x41UL<<0)
#define DEV_CMU_DBGCTL_SEL_PSRAM_MCLK                           (0x42UL<<0)
#define DEV_CMU_DBGCTL_SEL_PSRAM_CLK                            (0x43UL<<0)
#define DEV_CMU_DBGCTL_SEL_CAMERA_CLK                           (0x44UL<<0)
#define DEV_CMU_DBGCTL_SEL_MASK                                 (0x7fUL<<0)
/****CMU_DBGCTL end****/


/***********************************CMU_TESTCTL***********************************/
#define DEV_CMU_TESTCTL_P_TEST                                  (0x1UL<<8)
#define DEV_CMU_TESTCTL_USB_SOF                                 (0x1UL<<7)
#define DEV_CMU_TESTCTL_PLL_USB                                 (0x1UL<<6)
#define DEV_CMU_TESTCTL_PLL_AUDIO                               (0x1UL<<5)
#define DEV_CMU_TESTCTL_PLL_CORE                                (0x1UL<<4)
#define DEV_CMU_TESTCTL_OSC_USB                                 (0x1UL<<3)
#define DEV_CMU_TESTCTL_OSC_XTAL                                (0x1UL<<2)
#define DEV_CMU_TESTCTL_OSC_DEV                                 (0x1UL<<1)
#define DEV_CMU_TESTCTL_OSC_ADC                                 (0x1UL<<0)
/****CMU_TESTCTL end****/


/***********************************DEV_CMU register***********************************/
typedef struct
{

    __IO    uint32_t    CLKEN0;                                  /* 0x0    Clock Enable */
    __IO    uint32_t    CLKEN1;                                  /* 0x4    Clock Enable */
    uint32_t    RESERVED0[2];
    __IO    uint32_t    SYSCLK;                                  /* 0x10    System Clock */
    uint32_t    RESERVED1[3];
    __IO    uint32_t    SPInCLK[2];                              /* 0x20    SPI0 Clock */
    __IO    uint32_t    I2CnCLK[2];                              /* 0x28    I2C0 Clock */
    __IO    uint32_t    UARTnCLK[3];                             /* 0x30    UART0 Clock */
    __IO    uint32_t    NOR0CLK;                                 /* 0x3c    NOR0 Clock */
    __IO    uint32_t    PWMnCLK[8];                              /* 0x40    PWM0 Clock */
    __IO    uint32_t    TIMERnCLK[4];                            /* 0x60    Timer0 Clock */
    __IO    uint32_t    ADCCLK;                                  /* 0x70    Audio ADC Clock */
    __IO    uint32_t    DACCLK;                                  /* 0x74    Audio DAC Clock */
    __IO    uint32_t    ASInCLK[2];                              /* 0x78    Audio Serial Interface0 Clock */
    __IO    uint32_t    IRRXCLK;                                 /* 0x80    IRRX Clock */
    __IO    uint32_t    IRTXCLK;                                 /* 0x84    IRTX Clock */
    __IO    uint32_t    TICKCLK;                                 /* 0x88    TICK Clock */
    __IO    uint32_t    SDCCLK;                                  /* 0x8c    SD Controller Clock */
    __IO    uint32_t    USBCLK;                                  /* 0x90    USB Controller Clock */
    __IO    uint32_t    CP2CLK;                                  /* 0x94    Charge Pump Clock 2 */
    __IO    uint32_t    HSCALCLK;                                /* 0x98    Headset Calibration Clock */
    __IO    uint32_t    DLYCLK;                                  /* 0x9c    DMIC Delay Clock */
    __IO    uint32_t    CAMERACLK;                               /* 0xa0    CAMERA Clock */
    __IO    uint32_t    UART3CLK;                                /* 0xa4    UART3 Clock */
    __IO    uint32_t    PSRAMCLK;                                /* 0xa8    PSRAM Clock */
    uint32_t    RESERVED2[17];
    __IO    uint32_t    CLKDET;                                  /* 0xf0    Clock Detect */
    __I     uint32_t    CLKRDY;                                  /* 0xf4    Clock Ready */
    __IO    uint32_t    DBGCTL;                                  /* 0xf8    Debug Control */
    __IO    uint32_t    TESTCTL;                                 /* 0xfc    Test Control */
} DEV_CMU_RegDef;
/****DEV_CMU end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
