/**
* @file         spv40xx_cmu.h
* @brief        提供系统时钟配置api，实现所有模块时钟配置
* @details      Null
*
* @author       系统软件部 - t
* @date         2023-05-23 14:10
* @version      V0.1
* @copyright    Copyright (c) 2017-2023  SpaceTouch Inc.
* +v0.1
*   添加断言
*   添加获取模块时钟函数（暂时添加部分）
*/
#ifndef _HAL_CMU_H__
#define _HAL_CMU_H__

#include "platform.h"


typedef enum
{
    CMU_Clock_SYS       = 0UL,
    CMU_Clock_OSC_ADC   = 1UL,
    CMU_Clock_OSC_DEV   = 2UL,
    CMU_Clock_OSC_XTAL  = 3UL,
    CMU_Clock_OSC_PHY   = 4UL,
    CMU_Clock_PLL_USB   = 5UL,
    CMU_Clock_PLL_CORE  = 6UL,
    CMU_Clock_PLL_AUDIO = 7UL,
    CMU_Clock_EXT_AON   = 8UL,
    CMU_Clock_EXT_DEV   = 9UL,
    CMU_Clock_ADC_CLK   = 10UL
} cmu_clock_source_t;

typedef enum
{
    AUDIO_PLL_36P864M  = 0UL,
    AUDIO_PLL_49P152M  = 1UL,
    AUDIO_PLL_33P8688M = 2UL,
    AUDIO_PLL_45P1584M = 3UL,
} cmu_audio_pll_set_t;


typedef enum
{
    DMA_CLOCK_ENABLE = 1ULL << 0,
    GPIO_CLOCK_ENABLE = 1ULL << 1,
    EFUSE_CLOCK_ENABLE = 1ULL << 2,
    ASU_CLOCK_ENABLE = 1ULL << 3,
    EINT_CLOCK_ENABLE = 1ULL << 4,
    TIMER_CLOCK_ENABLE = 1ULL << 5,
    TICK_CLOCK_ENABLE = 1ULL << 6,
    SPI0_CLOCK_ENABLE = 1ULL << 7,
    SPI1_CLOCK_ENABLE = 1ULL << 8,
    UART0_CLOCK_ENABLE = 1ULL << 9,
    UART1_CLOCK_ENABLE = 1ULL << 10,
    UART2_CLOCK_ENABLE = 1ULL << 11,
    I2C0_CLOCK_ENABLE = 1ULL << 12,
    I2C1_CLOCK_ENABLE = 1ULL << 13,
    ASI0_CLOCK_ENABLE = 1ULL << 14,
    ASI1_CLOCK_ENABLE = 1ULL << 15,
    IRRX_CLOCK_ENABLE = 1ULL << 16,
    IRTX_CLOCK_ENABLE = 1ULL << 17,
    PWM_CLOCK_ENABLE = 1ULL << 18,
    SDC_CLOCK_ENABLE = 1ULL << 19,
    USB_CLOCK_ENABLE = 1ULL << 20,
    // Bit 21 is reserved
    ADC_CLOCK_ENABLE = 1ULL << 22,
    DAC_CLOCK_ENABLE = 1ULL << 23,
    SRC_CLOCK_ENABLE = 1ULL << 24,
    NPU_CLOCK_ENABLE = 1ULL << 25,
    UDSP_CLOCK_ENABLE = 1ULL << 26,
    AON_CLOCK_ENABLE = 1ULL << 27,
    CAMERA_CLOCK_ENABLE = 1ULL << 28,
    UART3_CLOCK_ENABLE = 1ULL << 29,
    MPU_CLOCK_ENABLE = 1ULL << 30,
    // Bit 31 is reserved
    CPU_CLOCK_ENABLE = 1ULL << 32,
    SYS_CLOCK_ENABLE = 1ULL << 33,
    NORC_CLOCK_ENABLE = 1ULL << 34,
    CACHE_CLOCK_ENABLE = 1ULL << 35,
    RAM0_CLOCK_ENABLE = 1ULL << 36,
    RAM1_CLOCK_ENABLE = 1ULL << 37,
    RAM2_CLOCK_ENABLE = 1ULL << 38,
    RAM3_CLOCK_ENABLE = 1ULL << 39,
    RAM4_CLOCK_ENABLE = 1ULL << 40,
    RAM5_CLOCK_ENABLE = 1ULL << 41,
    RAM6_CLOCK_ENABLE = 1ULL << 42,
    RAM7_CLOCK_ENABLE = 1ULL << 43,
    DEV_CLOCK_ENABLE = 1ULL << 44,
    HST_CLOCK_ENABLE = 1ULL << 45,
    MEM_CLOCK_ENABLE = 1ULL << 46,
    PSRAM_CLOCK_ENABLE = 1ULL << 47,
} ClockEnableBits;

typedef enum
{
    DMA_RST_ENABLE = 1ULL << 0,
    GPIO_RST_ENABLE = 1ULL << 1,
    EFUSE_RST_ENABLE = 1ULL << 2,
    ASU_RST_ENABLE = 1ULL << 3,
    EINT_RST_ENABLE = 1ULL << 4,
    TIMER_RST_ENABLE = 1ULL << 5,
    TICK_RST_ENABLE = 1ULL << 6,
    SPI0_RST_ENABLE = 1ULL << 7,
    SPI1_RST_ENABLE = 1ULL << 8,
    UART0_RST_ENABLE = 1ULL << 9,
    UART1_RST_ENABLE = 1ULL << 10,
    UART2_RST_ENABLE = 1ULL << 11,
    I2C0_RST_ENABLE = 1ULL << 12,
    I2C1_RST_ENABLE = 1ULL << 13,
    ASI0_RST_ENABLE = 1ULL << 14,
    ASI1_RST_ENABLE = 1ULL << 15,
    IRRX_RST_ENABLE = 1ULL << 16,
    IRTX_RST_ENABLE = 1ULL << 17,
    PWM_RST_ENABLE = 1ULL << 18,
    SDC_RST_ENABLE = 1ULL << 19,
    USB_RST_ENABLE = 1ULL << 20,
    // Bit 21 is reserved
    ADC_RST_ENABLE = 1ULL << 22,
    DAC_RST_ENABLE = 1ULL << 23,
    SRC_RST_ENABLE = 1ULL << 24,
    NPU_RST_ENABLE = 1ULL << 25,
    UDSP_RST_ENABLE = 1ULL << 26,
    AON_RST_ENABLE = 1ULL << 27,
    CAMERA_RST_ENABLE = 1ULL << 28,
    UART3_RST_ENABLE = 1ULL << 29,
    MPU_RST_ENABLE = 1ULL << 30,
    // Bit 31 is reserved
    CPU_RST_ENABLE = 1ULL << 32,
    SYS_RST_ENABLE = 1ULL << 33,
    NORC_RST_ENABLE = 1ULL << 34,
    CACHE_RST_ENABLE = 1ULL << 35,
    RAM0_RST_ENABLE = 1ULL << 36,
    RAM1_RST_ENABLE = 1ULL << 37,
    RAM2_RST_ENABLE = 1ULL << 38,
    RAM3_RST_ENABLE = 1ULL << 39,
    RAM4_RST_ENABLE = 1ULL << 40,
    RAM5_RST_ENABLE = 1ULL << 41,
    RAM6_RST_ENABLE = 1ULL << 42,
    RAM7_RST_ENABLE = 1ULL << 43,
    DEV_RST_ENABLE = 1ULL << 44,
    HST_RST_ENABLE = 1ULL << 45,
    MEM_RST_ENABLE = 1ULL << 46,
    PSRAM_RST_ENABLE = 1ULL << 47,
} RstEnableBits;

//上游时钟

int32_t cmu_set_oscdev();
uint32_t cmu_get_oscdev_state();

int32_t cmu_set_oscxtal_capacitance(uint32_t icapf, uint32_t icapc, uint32_t ocapf, uint32_t ocapc);
int32_t cmu_set_oscxtal_gmctl(uint32_t value);
int32_t cmu_set_oscxtal();
uint32_t cmu_get_oscxtal_state();

int32_t cmu_set_oscphy();
uint32_t cmu_get_oscphy_state();

int32_t cmu_set_pllusb();
uint32_t cmu_get_pllusb_state();
uint32_t cmu_set_clk_en(ClockEnableBits clockoption, uint8_t en);
uint32_t rmu_set_rst_en(RstEnableBits rmu_option, uint8_t en);
int32_t cmu_set_pllcore(cmu_clock_source_t source_clk, uint32_t freq_out_mhz);
uint32_t cmu_get_pllcore_state();
void cmu_set_audio_pll(cmu_audio_pll_set_t audio_pll_set);
typedef enum
{
    CMU_PLLADUIO_Output_11289600hz = 11289600UL,
    CMU_PLLADUIO_Output_12288000hz = 12288000UL,
    CMU_PLLADUIO_Output_22579200hz = 22579200UL,
    CMU_PLLADUIO_Output_24576000hz = 24576000UL,
    CMU_PLLADUIO_Output_33868800hz = 33868800UL,
    CMU_PLLADUIO_Output_36864000hz = 36864000UL,
    CMU_PLLADUIO_Output_45158400hz = 45158400UL,

} cmu_pllaudio_output_t;


int32_t cmu_set_pllaudio(cmu_clock_source_t source_clk, cmu_pllaudio_output_t pllaudio_out);
uint32_t cmu_get_pllaudio_state();


int32_t cmu_clk_ready_detect(cmu_clock_source_t source_clk);
int32_t cmu_get_clk_detect(cmu_clock_source_t source_clk);


//下游时钟

typedef enum
{
    CMU_Clk_Div_1 = 0UL,
    CMU_Clk_Div_2 = 1UL,
    CMU_Clk_Div_4 = 2UL,
    CMU_Clk_Div_8 = 3UL,
    CMU_Clk_Div_12 = 4UL,
    CMU_Clk_Div_16 = 5UL,
    CMU_Clk_Div_24 = 6UL,
    CMU_Clk_Div_32 = 7UL,
} cmu_clk_div_t;

int32_t cmu_sys_set_clk(cmu_clock_source_t source_clk, cmu_clk_div_t core_div_x, cmu_clk_div_t  sys_div_x);

int32_t cmu_spi_set_clk(uint32_t chx, cmu_clock_source_t source_clk, cmu_clk_div_t div_x);

int32_t cmu_i2c_set_clk(uint32_t chx, cmu_clock_source_t source_clk);

int32_t cmu_uart_set_clk(uint32_t chx, cmu_clock_source_t source_clk);

int32_t cmu_nor_set_clk(cmu_clock_source_t source_clk, cmu_clk_div_t div_x);

int32_t cmu_pwm_set_clk(uint32_t chx, cmu_clock_source_t source_clk, uint32_t divx);

int32_t cmu_timer_set_clk(uint32_t chx, cmu_clock_source_t source_clk);

int32_t cmu_adc_set_clk(cmu_clock_source_t source_clk, uint32_t divx);

typedef enum
{
    CMU_DAC_HscalCLK_128Khz = 0UL,
    CMU_DAC_HscalCLK_64Khz =  1UL,
    CMU_DAC_HscalCLK_32Khz =  2UL,
    CMU_DAC_HscalCLK_16Khz =  3UL,
    CMU_DAC_HscalCLK_8Khz =   4UL,
    CMU_DAC_HscalCLK_4Khz =   5UL,
    CMU_DAC_HscalCLK_2Khz =   6UL,
} cmu_dac_hscal_clk_t;

int32_t cmu_dac_set_clk(cmu_clock_source_t source_clk, uint32_t divx);
int32_t cmu_dac_cp2_set_clk(cmu_clock_source_t source_clk, uint32_t divx);
int32_t cmu_dac_hscal_set_clk(cmu_dac_hscal_clk_t clk_khz);

int32_t cmu_dly_set_clk(cmu_clock_source_t source_clk);


int32_t cmu_asi_set_clk(uint32_t chx, cmu_clock_source_t source_clk, uint32_t divx);

int32_t cmu_irrx_set_clk(cmu_clock_source_t source_clk, uint32_t divx);

int32_t cmu_irtx_set_clk(cmu_clock_source_t source_clk, uint32_t divx);

typedef enum
{
    CMU_TickClk_Div_4  = 0UL,
    CMU_TickClk_Div_16 = 1UL,
    CMU_TickClk_Div_24 = 2UL,
    CMU_TickClk_Div_30 = 3UL,
} cmu_tick_clk_div_t;
int32_t cmu_tick_set_clk(cmu_clock_source_t source_clk, cmu_tick_clk_div_t div_x);


int32_t cmu_camera_set_clk(cmu_clock_source_t source_clk, cmu_clk_div_t div_x);

int32_t cmu_param_set_clk(cmu_clock_source_t source_clk, cmu_clk_div_t div_x);

int32_t cmu_mpu_set_clk();
int32_t cmu_udsp_set_clk();
int32_t cmu_npu_set_clk();
int32_t cmu_eint_set_clk();
int32_t cmu_asu_set_clk();
int32_t cmu_efuse_set_clk();
int32_t cmu_gpio_set_clk();
int32_t cmu_dma_set_clk();
int32_t cmu_dma_reset_clk();
int32_t cmu_aon_set_clk();
uint32_t cmu_get_pllcore_clk(void);
int32_t cmu_aon_lradc_set_clk(cmu_clock_source_t source_clk, uint32_t divx);

int32_t cmu_aon_aduio_dmic_set_clk(cmu_clock_source_t source_clk, uint32_t divx);
int32_t cmu_aon_aduio_i2srx_set_clk(cmu_clock_source_t source_clk, uint32_t divx);
int32_t cmu_aon_aduio_set_clk();

int32_t cmu_aon_buff_set_clk();
uint32_t cmu_enable_usb_clock(void);

void cmu_clk_debugout(uint32_t source_clk, uint32_t div_x, uint32_t gpio_x);
void delay_ms(uint32_t cpu_clock, uint32_t ms);
void delay_us(uint32_t cpu_clock, uint32_t us);
uint32_t cmu_get_cpuclk();
uint32_t cmu_get_tickclk();
uint64_t get_mcycle(void);


#define IS_CMU_OSCXTAL_CAPF(VALUE)      (((VALUE)>=0UL)&&((VALUE)<=0X1FUL))
#define IS_CMU_OSCXTAL_CAPC(VALUE)      (((VALUE)>=0UL)&&((VALUE)<=0XFUL))
#define IS_CMU_OSCXTAL_GMCTL(VALUE)     (((VALUE)>=0UL)&&((VALUE)<=0XFUL))
#define IS_CMU_PLLCORE_OUT_MHZ(FREQ)    (((FREQ)>=36UL)&&((FREQ)<=762UL))

#define IS_CMU_PLLCORE_SRCCLK(CLK)      (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL) \
                                        ||((CLK)==CMU_Clock_OSC_PHY))

#define IS_CMU_PLLAUDIO_SRCCLK(CLK)     (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL) \
                                        ||((CLK)==CMU_Clock_OSC_PHY))

#define IS_CMU_DETECT_CLK(CLK)          (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL) \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        ||((CLK)==CMU_Clock_PLL_CORE)   \
                                        ||((CLK)==CMU_Clock_PLL_AUDIO)  \
                                        ||((CLK)==CMU_Clock_PLL_USB)    \
                                        ||((CLK)==CMU_Clock_EXT_DEV)    \
                                        ||((CLK)==CMU_Clock_EXT_AON)    \
                                        )

#define IS_CMU_SYS_SRCCLK(CLK)          (((CLK)==CMU_Clock_OSC_ADC) \
                                        ||((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        ||((CLK)==CMU_Clock_PLL_CORE)   \
                                        ||((CLK)==CMU_Clock_PLL_USB)    \
                                        )

#define IS_CMU_SPI_SRCCLK(CLK)          (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        ||((CLK)==CMU_Clock_PLL_CORE)   \
                                        )
#define IS_CMU_SPI_CHANNEL(CHX)         (((CHX)==0) \
                                        ||((CHX)==1) \
                                        )

#define IS_CMU_I2C_SRCCLK(CLK)          (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        )
#define IS_CMU_I2C_CHANNEL(CHX)         (((CHX)==0) \
                                        ||((CHX)==1) \
                                        )

#define IS_CMU_UART_SRCCLK(CLK)         (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        )
#define IS_CMU_UART_CHANNEL(CHX)        (((CHX)==0) \
                                        ||((CHX)==1) \
                                        ||((CHX)==2) \
                                        ||((CHX)==3) \
                                        )

#define IS_CMU_NOR_SRCCLK(CLK)          (((CLK)==CMU_Clock_SYS) \
                                        ||((CLK)==CMU_Clock_OSC_DEV)    \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        ||((CLK)==CMU_Clock_PLL_CORE)   \
                                        ||((CLK)==CMU_Clock_PLL_USB)    \
                                        )

#define IS_CMU_PWM_SRCCLK(CLK)          (((CLK)==CMU_Clock_OSC_ADC) \
                                        ||((CLK)==CMU_Clock_OSC_DEV)    \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        ||((CLK)==CMU_Clock_PLL_CORE)   \
                                        ||((CLK)==CMU_Clock_PLL_AUDIO)  \
                                        )
#define IS_CMU_PWM_CHANNEL(CHX)         (((CHX)==0) \
                                        ||((CHX)==1) \
                                        ||((CHX)==2) \
                                        ||((CHX)==3) \
                                        ||((CHX)==4) \
                                        ||((CHX)==5) \
                                        ||((CHX)==6) \
                                        ||((CHX)==7) \
                                        )
#define IS_CMU_PWM_DIV(DIVX)            (((DIVX)>=1UL)&&((DIVX)<=8192UL))


#define IS_CMU_TIMER_SRCCLK(CLK)        (((CLK)==CMU_Clock_OSC_ADC) \
                                        ||((CLK)==CMU_Clock_OSC_DEV)    \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        ||((CLK)==CMU_Clock_PLL_CORE)   \
                                        ||((CLK)==CMU_Clock_PLL_AUDIO)  \
                                        )
#define IS_CMU_TIMER_CHANNEL(CHX)       (((CHX)==0) \
                                        ||((CHX)==1) \
                                        ||((CHX)==2) \
                                        ||((CHX)==3) \
                                        )

#define IS_CMU_ADC_SRCCLK(CLK)          (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        ||((CLK)==CMU_Clock_PLL_AUDIO)  \
                                        )
#define IS_CMU_ADC_DIV(DIVX)            (((DIVX)>=1UL)&&((DIVX)<=256UL))


#define IS_CMU_DAC_SRCCLK(CLK)          (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        ||((CLK)==CMU_Clock_PLL_AUDIO)  \
                                        ||((CLK)==CMU_Clock_ADC_CLK)    \
                                        )
#define IS_CMU_DAC_DIV(DIVX)            (((DIVX)>=1UL)&&((DIVX)<=256UL))

#define IS_CMU_DAC_CP2_SRCCLK(CLK)      (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        )
#define IS_CMU_DAC_CP2_DIV(DIVX)        (((DIVX)>=1UL)&&((DIVX)<=16UL))

#define IS_CMU_DLY_SRCCLK(CLK)          (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        )

#define IS_CMU_ASI_SRCCLK(CLK)          (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        ||((CLK)==CMU_Clock_PLL_AUDIO)  \
                                        )
#define IS_CMU_ASI_CHANNEL(CHX)         (((CHX)==0) \
                                        ||((CHX)==1) \
                                        )
#define IS_CMU_ASI_DIV(DIVX)            (((DIVX)>=1UL)&&((DIVX)<=256UL))


#define IS_CMU_IRRX_SRCCLK(CLK)         (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        )
#define IS_CMU_IRRX_DIV(DIVX)           (((DIVX)>=1UL)&&((DIVX)<=256UL))


#define IS_CMU_IRTX_SRCCLK(CLK)         (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        )
#define IS_CMU_IRTX_DIV(DIVX)           (((DIVX)>=1UL)&&((DIVX)<=16UL))

#define IS_CMU_TICK_SRCCLK(CLK)         (((CLK)==CMU_Clock_SYS) \
                                        ||((CLK)==CMU_Clock_OSC_ADC)    \
                                        ||((CLK)==CMU_Clock_OSC_DEV)    \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        )

#define IS_CMU_CAMERA_SRCCLK(CLK)       (((CLK)==CMU_Clock_OSC_DEV) \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        ||((CLK)==CMU_Clock_PLL_CORE)   \
                                        )

#define IS_CMU_PSRAM_SRCCLK(CLK)        (((CLK)==CMU_Clock_SYS) \
                                        ||((CLK)==CMU_Clock_OSC_DEV)    \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        ||((CLK)==CMU_Clock_OSC_PHY)    \
                                        ||((CLK)==CMU_Clock_PLL_CORE)   \
                                        ||((CLK)==CMU_Clock_PLL_USB)    \
                                        )

#define IS_CMU_LRADC_SRCCLK(CLK)        (((CLK)==CMU_Clock_OSC_ADC) \
                                        ||((CLK)==CMU_Clock_OSC_DEV)    \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        )
#define IS_CMU_LRADC_DIV(DIVX)          (((DIVX)>=1UL)&&((DIVX)<=256UL))

#define IS_CMU_DMIC_SRCCLK(CLK)         (((CLK)==CMU_Clock_OSC_ADC) \
                                        ||((CLK)==CMU_Clock_OSC_DEV)    \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        )
#define IS_CMU_DMIC_DIV(DIVX)           (((DIVX)>=1UL)&&((DIVX)<=256UL))

#define IS_CMU_I2S_SRCCLK(CLK)          (((CLK)==CMU_Clock_OSC_ADC) \
                                        ||((CLK)==CMU_Clock_OSC_DEV)    \
                                        ||((CLK)==CMU_Clock_OSC_XTAL)   \
                                        )
#define IS_CMU_I2S_DIV(DIVX)            (((DIVX)>=1UL)&&((DIVX)<=256UL))


#endif
