#ifndef __AON_PMU_H__
#define __AON_PMU_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************PMU_PWR_CTL***********************************/
#define AON_PMU_PWR_CTL_CPP_DET_EN                              (0x1UL<<27)
#define AON_PMU_PWR_CTL_AVCC_DET_EN                             (0x1UL<<26)
#define AON_PMU_PWR_CTL_DVDD_DET_EN                             (0x1UL<<25)
#define AON_PMU_PWR_CTL_IOVCC_DET_EN                            (0x1UL<<24)
#define AON_PMU_PWR_CTL_CPP_FORCE_EN                            (0x1UL<<21)
#define AON_PMU_PWR_CTL_AVCC_FORCE_EN                           (0x1UL<<20)
#define AON_PMU_PWR_CTL_VDDQ_FORCE_EN                           (0x1UL<<19)
#define AON_PMU_PWR_CTL_DVDD_FORCE_EN                           (0x1UL<<18)
#define AON_PMU_PWR_CTL_IOVCC_FORCE_EN                          (0x1UL<<17)
#define AON_PMU_PWR_CTL_BIAS_FORCE_EN                           (0x1UL<<16)
#define AON_PMU_PWR_CTL_CPP_NORM_EN                             (0x1UL<<13)
#define AON_PMU_PWR_CTL_AVCC_NORM_EN                            (0x1UL<<12)
#define AON_PMU_PWR_CTL_VDDQ_NORM_EN                            (0x1UL<<11)
#define AON_PMU_PWR_CTL_DVDD_NORM_EN                            (0x1UL<<10)
#define AON_PMU_PWR_CTL_IOVCC_NORM_EN                           (0x1UL<<9)
#define AON_PMU_PWR_CTL_BIAS_NORM_EN                            (0x1UL<<8)
#define AON_PMU_PWR_CTL_PMU_SPEED_NORMAL                        (0x0UL<<4)
#define AON_PMU_PWR_CTL_PMU_SPEED_SPEEDFORTEST                  (0x1UL<<4)
#define AON_PMU_PWR_CTL_PMU_SPEED_MASK                          (0x1UL<<4)
#define AON_PMU_PWR_CTL_RESTART_TIME_100MS                      (0x0UL<<2)
#define AON_PMU_PWR_CTL_RESTART_TIME_250MS                      (0x1UL<<2)
#define AON_PMU_PWR_CTL_RESTART_TIME_500MS                      (0x2UL<<2)
#define AON_PMU_PWR_CTL_RESTART_TIME_1S                         (0x3UL<<2)
#define AON_PMU_PWR_CTL_RESTART_TIME_MASK                       (0x3UL<<2)
#define AON_PMU_PWR_CTL_STATE_ACTIVE                            (0x0UL<<0)
#define AON_PMU_PWR_CTL_STATE_STANDBY                           (0x1UL<<0)
#define AON_PMU_PWR_CTL_STATE_HIBERNATE                         (0x2UL<<0)
#define AON_PMU_PWR_CTL_STATE_RESTART                           (0x3UL<<0)
#define AON_PMU_PWR_CTL_STATE_MASK                              (0x3UL<<0)
/****PMU_PWR_CTL end****/


/***********************************PMU_VOL_CTL***********************************/
#define AON_PMU_VOL_CTL_AVDD_VOL_1_05V                          (0x0UL<<24)
#define AON_PMU_VOL_CTL_AVDD_VOL_1_10V                          (0x1UL<<24)
#define AON_PMU_VOL_CTL_AVDD_VOL_1_15V                          (0x2UL<<24)
#define AON_PMU_VOL_CTL_AVDD_VOL_1_20V                          (0x3UL<<24)
#define AON_PMU_VOL_CTL_AVDD_VOL_MASK                           (0x3UL<<24)
#define AON_PMU_VOL_CTL_CPP_VOL_1_70V                           (0x0UL<<20)
#define AON_PMU_VOL_CTL_CPP_VOL_1_75V                           (0x1UL<<20)
#define AON_PMU_VOL_CTL_CPP_VOL_1_80V                           (0x2UL<<20)
#define AON_PMU_VOL_CTL_CPP_VOL_1_85V                           (0x3UL<<20)
#define AON_PMU_VOL_CTL_CPP_VOL_MASK                            (0x3UL<<20)
#define AON_PMU_VOL_CTL_IOVCC_VOL_1_8V                          (0x0UL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_1_9V                          (0x1UL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_2_0V                          (0x2UL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_2_1V                          (0x3UL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_2_2V                          (0x4UL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_2_3V                          (0x5UL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_2_4V                          (0x6UL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_2_5V                          (0x7UL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_2_6V                          (0x8UL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_2_7V                          (0x9UL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_2_8V                          (0xaUL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_2_9V                          (0xbUL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_3_0V                          (0xcUL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_3_1V                          (0xdUL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_3_2V                          (0xeUL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_3_3V                          (0xfUL<<16)
#define AON_PMU_VOL_CTL_IOVCC_VOL_MASK                          (0xfUL<<16)
#define AON_PMU_VOL_CTL_AVCC_VOL_2_7V                           (0x0UL<<12)
#define AON_PMU_VOL_CTL_AVCC_VOL_2_8V                           (0x1UL<<12)
#define AON_PMU_VOL_CTL_AVCC_VOL_2_9V                           (0x2UL<<12)
#define AON_PMU_VOL_CTL_AVCC_VOL_3_0V                           (0x3UL<<12)
#define AON_PMU_VOL_CTL_AVCC_VOL_3_1V                           (0x4UL<<12)
#define AON_PMU_VOL_CTL_AVCC_VOL_3_2V                           (0x5UL<<12)
#define AON_PMU_VOL_CTL_AVCC_VOL_3_3V                           (0x6UL<<12)
#define AON_PMU_VOL_CTL_AVCC_VOL_3_4V                           (0x7UL<<12)
#define AON_PMU_VOL_CTL_AVCC_VOL_MASK                           (0x7UL<<12)
#define AON_PMU_VOL_CTL_DVDD_VOL_0_7V                           (0x0UL<<8)
#define AON_PMU_VOL_CTL_DVDD_VOL_0_8V                           (0x1UL<<8)
#define AON_PMU_VOL_CTL_DVDD_VOL_0_9V                           (0x2UL<<8)
#define AON_PMU_VOL_CTL_DVDD_VOL_1_0V                           (0x3UL<<8)
#define AON_PMU_VOL_CTL_DVDD_VOL_1_1V                           (0x4UL<<8)
#define AON_PMU_VOL_CTL_DVDD_VOL_1_2V                           (0x5UL<<8)
#define AON_PMU_VOL_CTL_DVDD_VOL_1_3V                           (0x6UL<<8)
#define AON_PMU_VOL_CTL_DVDD_VOL_1_4V                           (0x7UL<<8)
#define AON_PMU_VOL_CTL_DVDD_VOL_MASK                           (0x7UL<<8)
#define AON_PMU_VOL_CTL_SVDD_VOL_1_05V                          (0x0UL<<4)
#define AON_PMU_VOL_CTL_SVDD_VOL_1_10V                          (0x1UL<<4)
#define AON_PMU_VOL_CTL_SVDD_VOL_1_15V                          (0x2UL<<4)
#define AON_PMU_VOL_CTL_SVDD_VOL_1_20V                          (0x3UL<<4)
#define AON_PMU_VOL_CTL_SVDD_VOL_MASK                           (0x3UL<<4)
#define AON_PMU_VOL_CTL_SVCC_VOL_2_7V                           (0x0UL<<0)
#define AON_PMU_VOL_CTL_SVCC_VOL_2_8V                           (0x1UL<<0)
#define AON_PMU_VOL_CTL_SVCC_VOL_2_9V                           (0x2UL<<0)
#define AON_PMU_VOL_CTL_SVCC_VOL_3_0V                           (0x3UL<<0)
#define AON_PMU_VOL_CTL_SVCC_VOL_3_1V                           (0x4UL<<0)
#define AON_PMU_VOL_CTL_SVCC_VOL_3_2V                           (0x5UL<<0)
#define AON_PMU_VOL_CTL_SVCC_VOL_3_3V                           (0x6UL<<0)
#define AON_PMU_VOL_CTL_SVCC_VOL_3_4V                           (0x7UL<<0)
#define AON_PMU_VOL_CTL_SVCC_VOL_MASK                           (0x7UL<<0)
/****PMU_VOL_CTL end****/


/***********************************PMU_CLK_CTL***********************************/
#define AON_PMU_CLK_CTL_PLL_AUDIO_KEEP                          (0x1UL<<3)
#define AON_PMU_CLK_CTL_PLL_CORE_KEEP                           (0x1UL<<2)
#define AON_PMU_CLK_CTL_OSC_XTAL_KEEP                           (0x1UL<<1)
#define AON_PMU_CLK_CTL_OSC_DEV_KEEP                            (0x1UL<<0)
/****PMU_CLK_CTL end****/


/***********************************PMU_REF_TRIM***********************************/
#define AON_PMU_REF_TRIM_CMU_VBG2_TRIM_0_801V                   (0x0UL<<16)
#define AON_PMU_REF_TRIM_CMU_VBG2_TRIM_0_883V                   (0x1UL<<16)
#define AON_PMU_REF_TRIM_CMU_VBG2_TRIM_0_964V                   (0x2UL<<16)
#define AON_PMU_REF_TRIM_CMU_VBG2_TRIM_1_033V                   (0x3UL<<16)
#define AON_PMU_REF_TRIM_CMU_VBG2_TRIM_1_111V                   (0x4UL<<16)
#define AON_PMU_REF_TRIM_CMU_VBG2_TRIM_1_169V                   (0x5UL<<16)
#define AON_PMU_REF_TRIM_CMU_VBG2_TRIM_1_226V                   (0x6UL<<16)
#define AON_PMU_REF_TRIM_CMU_VBG2_TRIM_1_276V                   (0x7UL<<16)
#define AON_PMU_REF_TRIM_CMU_VBG2_TRIM_MASK                     (0x7UL<<16)
#define AON_PMU_REF_TRIM_VBG1_TRIM_1_779V                       (0x0UL<<12)
#define AON_PMU_REF_TRIM_VBG1_TRIM_1_787V                       (0x1UL<<12)
#define AON_PMU_REF_TRIM_VBG1_TRIM_1_794V                       (0x2UL<<12)
#define AON_PMU_REF_TRIM_VBG1_TRIM_1_801V                       (0x3UL<<12)
#define AON_PMU_REF_TRIM_VBG1_TRIM_1_809V                       (0x4UL<<12)
#define AON_PMU_REF_TRIM_VBG1_TRIM_1_816V                       (0x5UL<<12)
#define AON_PMU_REF_TRIM_VBG1_TRIM_1_823V                       (0x6UL<<12)
#define AON_PMU_REF_TRIM_VBG1_TRIM_1_829V                       (0x7UL<<12)
#define AON_PMU_REF_TRIM_VBG1_TRIM_MASK                         (0x7UL<<12)
#define AON_PMU_REF_TRIM_IREF_TRIM_MASK                         (0xfUL<<8)
#define AON_PMU_REF_TRIM_VREF_TRIM_MASK                         (0x1fUL<<0)
/****PMU_REF_TRIM end****/


/***********************************PMU_ONOFF***********************************/
#define AON_PMU_ONOFF_ONOFF_EDGE_NONE                           (0x0UL<<20)
#define AON_PMU_ONOFF_ONOFF_EDGE_RISE                           (0x1UL<<20)
#define AON_PMU_ONOFF_ONOFF_EDGE_FALL                           (0x2UL<<20)
#define AON_PMU_ONOFF_ONOFF_EDGE_BOTHEDGE                       (0x3UL<<20)
#define AON_PMU_ONOFF_ONOFF_EDGE_HIGH                           (0x4UL<<20)
#define AON_PMU_ONOFF_ONOFF_EDGE_LOW                            (0x5UL<<20)
#define AON_PMU_ONOFF_ONOFF_EDGE_MASK                           (0x7UL<<20)
#define AON_PMU_ONOFF_GPIO_SEL                                  (0x1UL<<18)
#define AON_PMU_ONOFF_ONOFF_SEL                                 (0x1UL<<17)
#define AON_PMU_ONOFF_ONOFF_SPEED                               (0x1UL<<16)
#define AON_PMU_ONOFF_ONOFF_LONG_TIME_4S                        (0x0UL<<12)
#define AON_PMU_ONOFF_ONOFF_LONG_TIME_8S                        (0x1UL<<12)
#define AON_PMU_ONOFF_ONOFF_LONG_TIME_12S                       (0x2UL<<12)
#define AON_PMU_ONOFF_ONOFF_LONG_TIME_16S                       (0x3UL<<12)
#define AON_PMU_ONOFF_ONOFF_LONG_TIME_MASK                      (0x3UL<<12)
#define AON_PMU_ONOFF_ONOFF_ULONG_TIME_12S                      (0x0UL<<11)
#define AON_PMU_ONOFF_ONOFF_ULONG_TIME_24S                      (0x1UL<<11)
#define AON_PMU_ONOFF_ONOFF_ULONG_TIME_MASK                     (0x1UL<<11)
#define AON_PMU_ONOFF_ONOFF_SHORT_TIME_125MS                    (0x0UL<<8)
#define AON_PMU_ONOFF_ONOFF_SHORT_TIME_250MS                    (0x1UL<<8)
#define AON_PMU_ONOFF_ONOFF_SHORT_TIME_500MS                    (0x2UL<<8)
#define AON_PMU_ONOFF_ONOFF_SHORT_TIME_1S                       (0x3UL<<8)
#define AON_PMU_ONOFF_ONOFF_SHORT_TIME_1_5S                     (0x4UL<<8)
#define AON_PMU_ONOFF_ONOFF_SHORT_TIME_2S                       (0x5UL<<8)
#define AON_PMU_ONOFF_ONOFF_SHORT_TIME_3S                       (0x6UL<<8)
#define AON_PMU_ONOFF_ONOFF_SHORT_TIME_4S                       (0x7UL<<8)
#define AON_PMU_ONOFF_ONOFF_SHORT_TIME_MASK                     (0x7UL<<8)
#define AON_PMU_ONOFF_ONOFF_DEB_TIME_25MS                       (0x0UL<<4)
#define AON_PMU_ONOFF_ONOFF_DEB_TIME_50MS                       (0x1UL<<4)
#define AON_PMU_ONOFF_ONOFF_DEB_TIME_75MS                       (0x2UL<<4)
#define AON_PMU_ONOFF_ONOFF_DEB_TIME_100MS                      (0x3UL<<4)
#define AON_PMU_ONOFF_ONOFF_DEB_TIME_MASK                       (0x3UL<<4)
#define AON_PMU_ONOFF_ONOFF_BOOT                                (0x1UL<<3)
#define AON_PMU_ONOFF_ONOFF_DEB_PRESS                           (0x0UL<<2)
#define AON_PMU_ONOFF_ONOFF_DEB_NOPRESS                         (0x1UL<<2)
#define AON_PMU_ONOFF_ONOFF_DEB_MASK                            (0x1UL<<2)
#define AON_PMU_ONOFF_PWR_STA_ONOFFWAKEUP                       (0x0UL<<1)
#define AON_PMU_ONOFF_PWR_STA_FIRSTPOWERUP                      (0x1UL<<1)
#define AON_PMU_ONOFF_PWR_STA_MASK                              (0x1UL<<1)
#define AON_PMU_ONOFF_ONOFF_IN_PRESS                            (0x0UL<<0)
#define AON_PMU_ONOFF_ONOFF_IN_NOPRESS                          (0x1UL<<0)
#define AON_PMU_ONOFF_ONOFF_IN_MASK                             (0x1UL<<0)
/****PMU_ONOFF end****/


/***********************************PMU_PWR_STA***********************************/
#define AON_PMU_PWR_STA_CPPOK                                   (0x1UL<<3)
#define AON_PMU_PWR_STA_IOVCCOK                                 (0x1UL<<2)
#define AON_PMU_PWR_STA_AVCCOK                                  (0x1UL<<1)
#define AON_PMU_PWR_STA_DVDDOK                                  (0x1UL<<0)
/****PMU_PWR_STA end****/


/***********************************PMU_IE***********************************/
#define AON_PMU_IE_SPIO_INT                                     (0x1UL<<5)
#define AON_PMU_IE_ONOFF_EDGE                                   (0x1UL<<4)
#define AON_PMU_IE_ONOFF_XLONG                                  (0x1UL<<3)
#define AON_PMU_IE_ONOFF_ULONG                                  (0x1UL<<2)
#define AON_PMU_IE_ONOFF_LONG                                   (0x1UL<<1)
#define AON_PMU_IE_ONOFF_SHORT                                  (0x1UL<<0)
/****PMU_IE end****/


/***********************************PMU_PD***********************************/
#define AON_PMU_PD_SPIO_INT                                     (0x1UL<<5)
#define AON_PMU_PD_ONOFF_EDGE                                   (0x1UL<<4)
#define AON_PMU_PD_ONOFF_XLONG                                  (0x1UL<<3)
#define AON_PMU_PD_ONOFF_ULONG                                  (0x1UL<<2)
#define AON_PMU_PD_ONOFF_LONG                                   (0x1UL<<1)
#define AON_PMU_PD_ONOFF_SHORT                                  (0x1UL<<0)
/****PMU_PD end****/


/***********************************PMU_WKEN***********************************/
#define AON_PMU_WKEN_SPIO_INT                                   (0x1UL<<5)
#define AON_PMU_WKEN_ONOFF_EDGE                                 (0x1UL<<4)
#define AON_PMU_WKEN_ONOFF_XLONG                                (0x1UL<<3)
#define AON_PMU_WKEN_ONOFF_ULONG                                (0x1UL<<2)
#define AON_PMU_WKEN_ONOFF_LONG                                 (0x1UL<<1)
#define AON_PMU_WKEN_ONOFF_SHORT                                (0x1UL<<0)
/****PMU_WKEN end****/


/***********************************PMU_RSTEN***********************************/
#define AON_PMU_RSTEN_RESTART_SVDD                              (0x1UL<<12)
#define AON_PMU_RSTEN_RESTART_XLONG                             (0x1UL<<11)
#define AON_PMU_RSTEN_RESTART_ULONG                             (0x1UL<<10)
#define AON_PMU_RSTEN_RESTART_LONG                              (0x1UL<<9)
#define AON_PMU_RSTEN_RESTART_SHORT                             (0x1UL<<8)
#define AON_PMU_RSTEN_RESET_SVDD                                (0x1UL<<4)
#define AON_PMU_RSTEN_RESET_XLONG                               (0x1UL<<3)
#define AON_PMU_RSTEN_RESET_ULONG                               (0x1UL<<2)
#define AON_PMU_RSTEN_RESET_LONG                                (0x1UL<<1)
#define AON_PMU_RSTEN_RESET_SHORT                               (0x1UL<<0)
/****PMU_RSTEN end****/


/***********************************AON_PMU register***********************************/
typedef struct
{
    __IO    uint32_t    PWR_CTL;                                 /* 0x0    PMU Power Control */
    __IO    uint32_t    VOL_CTL;                                 /* 0x4    PMU Voltage Control */
    __IO    uint32_t    CLK_CTL;                                 /* 0x8    PMU Clock Control */
    __IO    uint32_t    REF_TRIM;                                /* 0xc    PMU Reference Control */
    __IO    uint32_t    ONOFF;                                   /* 0x10    PMU Onoff Control */
    __IO    uint32_t    PWR_STA;                                 /* 0x14    PMU Status */
    uint32_t    RESERVED0[2];
    __IO    uint32_t    IE;                                      /* 0x20    PMU Interrupt Control */
    __IO    uint32_t    PD;                                      /* 0x24    PMU Pending */
    __IO    uint32_t    WKEN;                                    /* 0x28    PMU Reset Control */
    __IO    uint32_t    RSTEN;                                   /* 0x2c    PMU Wakeup */
} AON_PMU_RegDef;
/****AON_PMU end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
