#ifndef __DEV_NORC_H__
#define __DEV_NORC_H__

#include "sp2cw3.h"

/*******************************************************************************
 * Auto-generated Content
 ******************************************************************************/


/***********************************NORC_CTL***********************************/
#define DEV_NORC_CTL_DUAL_WIDTH                                 (0x1UL<<31)
#define DEV_NORC_CTL_DUAL_DEPTH                                 (0x1UL<<30)
#define DEV_NORC_CTL_SOFT_CONT_DISABLE                          (0x0UL<<29)
#define DEV_NORC_CTL_SOFT_CONT_ENABLE                           (0x1UL<<29)
#define DEV_NORC_CTL_SOFT_CONT_MASK                             (0x1UL<<29)
#define DEV_NORC_CTL_CACH_CONT_DISABLE                          (0x0UL<<28)
#define DEV_NORC_CTL_CACH_CONT_ENABLE                           (0x1UL<<28)
#define DEV_NORC_CTL_CACH_CONT_MASK                             (0x1UL<<28)
#define DEV_NORC_CTL_UNCA_CONT_DISABLE                          (0x0UL<<27)
#define DEV_NORC_CTL_UNCA_CONT_ENABLE                           (0x1UL<<27)
#define DEV_NORC_CTL_UNCA_CONT_MASK                             (0x1UL<<27)
#define DEV_NORC_CTL_PREF_MODE_AUTO                             (0x0UL<<26)
#define DEV_NORC_CTL_PREF_MODE_FIX                              (0x1UL<<26)
#define DEV_NORC_CTL_PREF_MODE_MASK                             (0x1UL<<26)
#define DEV_NORC_CTL_PREF_EN_DISABLE                            (0x0UL<<25)
#define DEV_NORC_CTL_PREF_EN_ENABLE                             (0x1UL<<25)
#define DEV_NORC_CTL_PREF_EN_MASK                               (0x1UL<<25)
#define DEV_NORC_CTL_NOR_WAIT_RUN                               (0x0UL<<24)
#define DEV_NORC_CTL_NOR_WAIT_WAIT                              (0x1UL<<24)
#define DEV_NORC_CTL_NOR_WAIT_MASK                              (0x1UL<<24)
#define DEV_NORC_CTL_SPI_MODE_MODE0                             (0x0UL<<22)
#define DEV_NORC_CTL_SPI_MODE_MODE1                             (0x1UL<<22)
#define DEV_NORC_CTL_SPI_MODE_MODE2                             (0x2UL<<22)
#define DEV_NORC_CTL_SPI_MODE_MODE3                             (0x3UL<<22)
#define DEV_NORC_CTL_SPI_MODE_MASK                              (0x3UL<<22)
#define DEV_NORC_CTL_STOP_CYCLE_1                               (0x0UL<<20)
#define DEV_NORC_CTL_STOP_CYCLE_2                               (0x1UL<<20)
#define DEV_NORC_CTL_STOP_CYCLE_3                               (0x2UL<<20)
#define DEV_NORC_CTL_STOP_CYCLE_4                               (0x3UL<<20)
#define DEV_NORC_CTL_STOP_CYCLE_MASK                            (0x3UL<<20)
#define DEV_NORC_CTL_HOLD_CYCLE_4                               (0x0UL<<18)
#define DEV_NORC_CTL_HOLD_CYCLE_16                              (0x1UL<<18)
#define DEV_NORC_CTL_HOLD_CYCLE_64                              (0x2UL<<18)
#define DEV_NORC_CTL_HOLD_CYCLE_256                             (0x3UL<<18)
#define DEV_NORC_CTL_HOLD_CYCLE_MASK                            (0x3UL<<18)
#define DEV_NORC_CTL_HOLD_MODE_DISABLE                          (0x0UL<<17)
#define DEV_NORC_CTL_HOLD_MODE_ENABLE                           (0x1UL<<17)
#define DEV_NORC_CTL_HOLD_MODE_MASK                             (0x1UL<<17)
#define DEV_NORC_CTL_DELAY_CHAIN_MASK                           (0x1fUL<<12)
#define DEV_NORC_CTL_DUMY_CYCLE_MASK                            (0xfUL<<8)
#define DEV_NORC_CTL_WAIT_CYCLE_MASK                            (0x3UL<<6)
#define DEV_NORC_CTL_DDR_MODE_SINGLEEDGE                        (0x0UL<<5)
#define DEV_NORC_CTL_DDR_MODE_DOUBLEEDGE                        (0x1UL<<5)
#define DEV_NORC_CTL_DDR_MODE_MASK                              (0x1UL<<5)
#define DEV_NORC_CTL_DIO_MODE_MOSI_AND_MISOSEPARATE             (0x0UL<<4)
#define DEV_NORC_CTL_DIO_MODE_3WIRESPI                          (0x1UL<<4)
#define DEV_NORC_CTL_DIO_MODE_MASK                              (0x1UL<<4)
#define DEV_NORC_CTL_FAST_MODE_NORMALMODE                       (0x0UL<<3)
#define DEV_NORC_CTL_FAST_MODE_FASTMODE                         (0x1UL<<3)
#define DEV_NORC_CTL_FAST_MODE_MASK                             (0x1UL<<3)
#define DEV_NORC_CTL_ADR_MODE_SINGLE                            (0x0UL<<2)
#define DEV_NORC_CTL_ADR_MODE_ACCORDINGTOSPI_WIDTH              (0x1UL<<2)
#define DEV_NORC_CTL_ADR_MODE_MASK                              (0x1UL<<2)
#define DEV_NORC_CTL_SPI_WIDTH_SINGLE                           (0x0UL<<0)
#define DEV_NORC_CTL_SPI_WIDTH_DUAL                             (0x1UL<<0)
#define DEV_NORC_CTL_SPI_WIDTH_QUAD                             (0x2UL<<0)
#define DEV_NORC_CTL_SPI_WIDTH_MASK                             (0x3UL<<0)
/****NORC_CTL end****/


/***********************************NORC_SOFT_CTL***********************************/
#define DEV_NORC_SOFT_CTL_CMD_DAT_MASK                          (0xffUL<<4)
#define DEV_NORC_SOFT_CTL_CMD_NSS_NSSIDLE                       (0x0UL<<3)
#define DEV_NORC_SOFT_CTL_CMD_NSS_NSSACTIVE                     (0x1UL<<3)
#define DEV_NORC_SOFT_CTL_CMD_NSS_MASK                          (0x1UL<<3)
#define DEV_NORC_SOFT_CTL_CMD_STA_IDLE                          (0x0UL<<2)
#define DEV_NORC_SOFT_CTL_CMD_STA_WORK                          (0x1UL<<2)
#define DEV_NORC_SOFT_CTL_CMD_STA_MASK                          (0x1UL<<2)
#define DEV_NORC_SOFT_CTL_BUFF_CLR_WORK                         (0x0UL<<1)
#define DEV_NORC_SOFT_CTL_BUFF_CLR_CLEAR                        (0x1UL<<1)
#define DEV_NORC_SOFT_CTL_BUFF_CLR_MASK                         (0x1UL<<1)
#define DEV_NORC_SOFT_CTL_SOFT_STA_STOP                         (0x0UL<<0)
#define DEV_NORC_SOFT_CTL_SOFT_STA_START                        (0x1UL<<0)
#define DEV_NORC_SOFT_CTL_SOFT_STA_MASK                         (0x1UL<<0)
/****NORC_SOFT_CTL end****/


/***********************************NORC_SOFT_STA***********************************/
#define DEV_NORC_SOFT_STA_BUS_IDLE                              (0x1UL<<5)
#define DEV_NORC_SOFT_STA_EMPTY                                 (0x1UL<<4)
#define DEV_NORC_SOFT_STA_FIFO_LEVEL_MASK                       (0xfUL<<0)
/****NORC_SOFT_STA end****/


/***********************************NORC_SOFT_BASE***********************************/
#define DEV_NORC_SOFT_BASE_BASE_ADDR_MASK                       (0x3ffffffUL<<0)
/****NORC_SOFT_BASE end****/


/***********************************NORC_SOFT_LEN***********************************/
#define DEV_NORC_SOFT_LEN_LENGTH_MASK                           (0x3ffffffUL<<0)
/****NORC_SOFT_LEN end****/


/***********************************NORC_SOFT_CNT***********************************/
#define DEV_NORC_SOFT_CNT_COUNTER_MASK                          (0x3ffffffUL<<0)
/****NORC_SOFT_CNT end****/


/***********************************NORC_SOFT_DATA***********************************/
#define DEV_NORC_SOFT_DATA_MASK                                 (0xffffffffUL<<0)
/****NORC_SOFT_DATA end****/


/***********************************NORC_SOFT_PD***********************************/
#define DEV_NORC_SOFT_PD_FIFO_UF_PD                             (0x1UL<<2)
#define DEV_NORC_SOFT_PD_LENGTH_PD                              (0x1UL<<1)
#define DEV_NORC_SOFT_PD_BLOCK_PD                               (0x1UL<<0)
/****NORC_SOFT_PD end****/


/***********************************NORC_SOFT_IE***********************************/
#define DEV_NORC_SOFT_IE_DMA_EN                                 (0x1UL<<16)
#define DEV_NORC_SOFT_IE_FIFO_UF_IE                             (0x1UL<<2)
#define DEV_NORC_SOFT_IE_LENGTH_IE                              (0x1UL<<1)
#define DEV_NORC_SOFT_IE_BLOCK_IE                               (0x1UL<<0)
/****NORC_SOFT_IE end****/


/***********************************NORC_ENCRY_CTL***********************************/
#define DEV_NORC_ENCRY_CTL_ALG_DIRECTXOR                        (0x0UL<<5)
#define DEV_NORC_ENCRY_CTL_ALG_ROUNDXOR                         (0x1UL<<5)
#define DEV_NORC_ENCRY_CTL_ALG_MASK                             (0x1UL<<5)
#define DEV_NORC_ENCRY_CTL_EN1                                  (0x1UL<<1)
#define DEV_NORC_ENCRY_CTL_EN0                                  (0x1UL<<0)
/****NORC_ENCRY_CTL end****/


/***********************************NORC_ENCRY_SEED***********************************/
#define DEV_NORC_ENCRY_SEED_MASK                                (0xffffffffUL<<0)
/****NORC_ENCRY_SEED end****/


/***********************************NORC_ENCRY_BASE0***********************************/
#define DEV_NORC_ENCRY_BASE0_ADDR_MASK                          (0x3fffUL<<12)
/****NORC_ENCRY_BASE0 end****/


/***********************************NORC_ENCRY_END0***********************************/
#define DEV_NORC_ENCRY_END0_ADDR_MASK                           (0x3fffUL<<12)
/****NORC_ENCRY_END0 end****/


/***********************************NORC_ENCRY_BASE1***********************************/
#define DEV_NORC_ENCRY_BASE1_ADDR_MASK                          (0x3fffUL<<12)
/****NORC_ENCRY_BASE1 end****/


/***********************************NORC_ENCRY_END1***********************************/
#define DEV_NORC_ENCRY_END1_ADDR_MASK                           (0x3fffUL<<12)
/****NORC_ENCRY_END1 end****/


/***********************************NORC_PERF_CTL***********************************/
#define DEV_NORC_PERF_CTL_SEL_TX_CYCLE                          (0x0UL<<2)
#define DEV_NORC_PERF_CTL_SEL_RX_CYCLE                          (0x1UL<<2)
#define DEV_NORC_PERF_CTL_SEL_MASK                              (0x1UL<<2)
#define DEV_NORC_PERF_CTL_STA                                   (0x1UL<<1)
#define DEV_NORC_PERF_CTL_EN                                    (0x1UL<<0)
/****NORC_PERF_CTL end****/


/***********************************NORC_PERF_SUM***********************************/
#define DEV_NORC_PERF_SUM_DATA_MASK                             (0xffffffffUL<<0)
/****NORC_PERF_SUM end****/


/***********************************NORC_PERF_CNT***********************************/
#define DEV_NORC_PERF_CNT_DATA_MASK                             (0xffffffffUL<<0)
/****NORC_PERF_CNT end****/


/***********************************DEV_NORC register***********************************/
typedef struct
{

    __IO    uint32_t    CTL;                                     /* 0x0    NORCTRL Control */
    __IO    uint32_t    SOFT_CTL;                                /* 0x4    Software Control */
    __I     uint32_t    SOFT_STA;                                /* 0x8    Software STATUS */
    __IO    uint32_t    SOFT_BASE;                               /* 0xc    Software Base Address */
    __IO    uint32_t    SOFT_LEN;                                /* 0x10    Software Length */
    __I     uint32_t    SOFT_CNT;                                /* 0x14    Software Counter */
    __I     uint32_t    SOFT_DATA;                               /* 0x18    Software Data */
    uint32_t    RESERVED0;
    __IO    uint32_t    SOFT_PD;                                 /* 0x20    Software Pending */
    __IO    uint32_t    SOFT_IE;                                 /* 0x24    Software Interrupt Enable */
    uint32_t    RESERVED1[2];
    __IO    uint32_t    ENCRY_CTL;                               /* 0x30    Encrypt Control */
    __O     uint32_t    ENCRY_SEED;                              /* 0x34    Encrypt Seed */
    __IO    uint32_t    ENCRY_BASE0;                             /* 0x38    Encrypt Area0 Start Address */
    __IO    uint32_t    ENCRY_END0;                              /* 0x3c    Encrypt Area0 End Address */
    __IO    uint32_t    ENCRY_BASE1;                             /* 0x40    Encrypt Area1 Start Address */
    __IO    uint32_t    ENCRY_END1;                              /* 0x44    Encrypt Area1 End Address */
    uint32_t    RESERVED2[2];
    __IO    uint32_t    PERF_CTL;                                /* 0x50    Performance Control */
    __I     uint32_t    PERF_SUM;                                /* 0x54    Performance Summary */
    __I     uint32_t    PERF_CNT;                                /* 0x58    Performance Counter */
} DEV_NORC_RegDef;
/****DEV_NORC end****/

/*******************************************************************************
 * User-defined Contents
 ******************************************************************************/



#endif
